www.ti.com |
|
|
53 | Receive CPPI DMA State Word 1 (RCPPIDMASTATEW1) | 106 |
54 | Receive CPPI DMA State Word 2 (RCPPIDMASTATEW2) | 107 |
55 | Receive CPPI DMA State Word 3 (RCPPIDMASTATEW3) | 107 |
56 | Receive CPPI DMA State Word 4 (RCPPIDMASTATEW4) | 109 |
57 | Receive CPPI DMA State Word 5 (RCPPIDMASTATEW5) | 109 |
58 | Receive CPPI DMA State Word 6 (RCPPIDMASTATEW6) | 110 |
59 | Receive CPPI Completion Pointer (RCPPICOMPPTR) | 110 |
60 | Function Address Register (FADDR) | 111 |
61 | Power Management Register (POWER) | 111 |
62 | Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 (INTRTX) | 112 |
63 | Interrupt Register for Receive Endpoints 1 to 4 (INTRRX) | 113 |
64 | Interrupt Enable Register for INTRTX (INTRTXE) | 113 |
65 | Interrupt Enable Register for INTRRX (INTRRXE) | 114 |
66 | Interrupt Register for Common USB Interrupts (INTRUSB) | 115 |
67 | Interrupt Enable Register for INTRUSB (INTRUSBE) | 116 |
68 | Frame Number Register (FRAME) | 117 |
69 | Index Register for Selecting the Endpoint Status and Control Registers (INDEX) | 117 |
70 | Register to Enable the USB 2.0 Test Modes (TESTMODE) | 118 |
71 | Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP) | 119 |
72 | Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0) | 120 |
73 | Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0) | 121 |
74 | Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR) | 122 |
75 | Control Status Register for Host Transmit Endpoint (HOST_TXCSR) | 123 |
76 | Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) | 124 |
77 | Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) | 125 |
78 | Control Status Register for Host Receive Endpoint (HOST_RXCSR) | 126 |
79 | Count 0 Register (COUNT0) | 128 |
80 | Receive Count Register (RXCOUNT) | 128 |
81 | Type Register (Host mode only) (HOST_TYPE0) | 129 |
82 | Transmit Type Register (Host mode only) (HOST_TXTYPE) | 129 |
83 | NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0) | 130 |
84 | Transmit Interval Register (Host mode only) (HOST_TXINTERVAL) | 130 |
85 | Receive Type Register (Host mode only) (HOST_RXTYPE) | 131 |
86 | Receive Interval Register (Host mode only) (HOST_RXINTERVAL) | 131 |
87 | Configuration Data Register (CONFIGDATA) | 132 |
88 | Transmit and Receive FIFO Register for Endpoint 0 (FIFO0) | 134 |
89 | Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) | 135 |
90 | Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) | 135 |
91 | Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) | 136 |
92 | Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) | 136 |
93 | OTG Device Control Register (DEVCTL) | 137 |
94 | Transmit Endpoint FIFO Size (TXFIFOSZ) | 138 |
95 | Receive Endpoint FIFO Size (RXFIFOSZ) | 138 |
96 | Transmit Endpoint FIFO Address (TXFIFOADDR) | 139 |
97 | Receive Endpoint FIFO Address (RXFIFOADDR) | 139 |
98 | Transmit Function Address (TXFUNCADDR) | 140 |
99 | Transmit Hub Address (TXHUBADDR) | 140 |
100 | Transmit Hub Port (TXHUBPORT) | 140 |
101 | Receive Function Address (RXFUNCADDR) | 141 |
102 | Receive Hub Address (RXHUBADDR) | 141 |
103 | Receive Hub Port (RXHUBPORT) | 141 |
List of Figures | 7 |
