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Texas Instruments TMS320DM357 manual 124

Models: TMS320DM357

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4.61 Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)

The Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) is shown in Figure 76 and described in Table 77.

Figure 76. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)

15	11	10	0
	Reserved		MAXPAYLOAD
	R-0		R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 77. Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP) Field Descriptions

Bit	Field	Value	Description
15-11	Reserved	0	Reserved
10-0	MAXPAYLOAD	0-FFh	Defines the maximum amount of data that can be transferred through the selected Receive
			endpoint in a single frame/microframe (high-speed transfers). The value set can be up to 1024
			bytes, but is subject to the constraints placed by the USB Specification on packet sizes for Bulk,
			Interrupt, and Isochronous transfers in full-speed and high-speed operations. The value written to
			this register should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the
			associated endpoint. A mismatch could cause unexpected results.

124

Universal Serial Bus (USB) Controller

SPRUGH3–November 2008

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Texas Instruments TMS320DM357 manual 124

Contents

Users Guide Submit Documentation Feedback Contents 100 Type Register Host mode only HOSTTYPE0 Appendix aList of Figures Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 List of Tables Function Address Register Faddr Field Descriptions Document Revision History Read This First Related Documentation From Texas InstrumentsNotational Conventions Notational Conventions Features Not Supported FeaturesPurpose of the Peripheral Functional Block Diagram CppiSupported Use Case Examples Example 1. Initializing the USB ControllerExample 2. Programming the USB Endpoints in Peripheral Mode Example 3. Programming the USB Endpoints in Host Mode Else Example 4. Programming the USB DMA Controller While usbRegs-PERITXCSR Industry Standards Compliance Statement Signal Descriptions USB PinsClock Control Indexed and Non-Indexed RegistersUSB PHY Initialization Dynamic Fifo SizingInterrupt Service Routine Flow Chart USB Controller Peripheral Mode Operation Peripheral Mode Control TransactionsZero Data Requests Write RequestsRead Requests CPU Actions at Transfer Phases Endpoint 0 StatesSequence of Transfer OUTEndpoint 0 Service Routine Service Endpoint 0 Flow Chart = IdleIdle Mode Idle Mode Flow ChartTX Mode TX Mode Flow ChartRX Mode RX Mode Flow ChartError Handling Additional ConditionsPeripheral Mode Bulk In Transactions SetupBit Position Bit Field Name Configuration Bulk TransactionsPeripheral Mode Bulk OUT Transactions OperationDisnyet Interrupt Transactions Isochronous Transactions Isochronous in TransactionsIsochronous OUT Transactions Set to 1 to enable isochronous protocol USB Controller Host Mode Operation Host Mode Control TransactionsSetup Phase Setup Phase of a Control Transaction Flow ChartData Phase RxpktrdyData Phase Flow Chart OUT Data PhaseOUT Data Phase Flow Chart Status Phase following Setup Phase or OUT Data Phase Completion of Setup or OUT Data Phase Flow ChartOUT Status Phase following in Data Phase Completion of in Data Phase Flow Chart Host Mode Bulk in Transactions Bulk OUT Transactions Host Mode Interrupt Transactions Host Mode Isochronous in Transactions Host Mode Isochronous Out Transactions DMA Operation DMA Transmit OperationTransmit Buffer Cppi Transmit Buffer DescriptorTransmit Buffer Descriptor Word Bits Name DescriptionBits Name Description 310 Buffer Pointer Descriptor. The software sets the Buffer PointerTransmit DMA State EOQTransmit Queue OperationTransparent Mode and Rndis Mode Transmit DMA Operation Rndis Mode Setup Transparent Mode SetupDMA Channel TearDown DMA Receive OperationCppi Receive Buffer Descriptor Receive Buffer Descriptor WordReceive DMA State Bit FieldRx Queue Flow Chart Receive QueueUSB Controller Host and Peripheral Modes Operation Rndis Mode and Transparent Mode Receive DMA Operation Receive Abort HandlingDMA Teardown Procedure Interrupt HandlingInterrupts Generated by the USB Controller USB Interrupt ConditionsUSB Interrupt Conditions USB Core Interrupts Test ModesDMA Interrupts Testj TESTSE0NAKTestk Testpacket Forcehost Reset Considerations Power ManagementInterrupt Support Edma Event SupportAcronym Register Description Universal Serial Bus USB RegistersTransmit/Receive Cppi Channel 0 State Block Offset Acronym Register Description Common USB Registers FIFOn Target Endpoint 1 Control Registers, Valid Only in Host Mode Target Endpoint 4 Control Registers, Valid Only in Host Mode Control and Status Register for Endpoint51Dh Control Register Ctrlr Field Descriptions Control Register CtrlrBit Field Value Description Status Register Statr Rndis Register RndisrStatus Register Statr Field Descriptions Rndis Register Rndisr Field DescriptionsAuto Request Register Autoreq Auto Request Register Autoreq Field DescriptionsUSB Interrupt Source Register Intsrcr Field Descriptions USB Interrupt Source Register IntsrcrUSB USB Interrupt Source Set Register Intsetr USB Interrupt Source Set Register IntsetrUSB Interrupt Source Clear Register Intclrr USB Interrupt Source Clear Register IntclrrUSB Interrupt Mask Register Intmskr USB Interrupt Mask Register Intmskr Field DescriptionsUSB Interrupt Mask Set Register Intmsksetr USB Interrupt Mask Set Register IntmsksetrUSB Interrupt Mask Clear Register Intmskclrr USB Interrupt Mask Clear Register IntmskclrrUSB Interrupt Source Masked Register Intmaskedr USB Interrupt Source Masked Register IntmaskedrUSB End of Interrupt Register Eoir USB Interrupt Vector Register IntvectrUSB End of Interrupt Register Eoir Field Descriptions USB Interrupt Vector Register Intvectr Field DescriptionsTransmit Cppi Control Register Tcppicr Transmit Cppi Teardown Register TcppitdrTransmit Cppi Control Register Tcppicr Field Descriptions Transmit Cppi Teardown Register Tcppitdr Field DescriptionsCppi DMA End of Interrupt Register Cppieoir Cppi DMA End of Interrupt Register CppieoirTransmit Cppi Masked Status Register Tcppimsksr Transmit Cppi Raw Status Register TcppirawsrMasked Comppending ComppendingTransmit Cppi Interrupt Enable Clear Register Tcppiienclrr Transmit Cppi Interrupt Enable Set Register TcppiiensetrComppendingintren Rcppienable Receive Cppi Control Register RcppicrReceive Cppi Masked Status Register Rcppimsksr Receive Cppi Control Register Rcppicr Field DescriptionsReceive Cppi Interrupt Enable Set Register Rcppiensetr Receive Cppi Raw Status Register RcppirawsrReceive Cppi Interrupt Enable Clear Register Rcppiienclrr Receive Buffer Count 0 Register RBUFCNT0Receive Buffer Count 0 Register RBUFCNT0 Field Descriptions BufcntReceive Buffer Count 1 Register RBUFCNT1 Receive Buffer Count 2 Register RBUFCNT2Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions Receive Buffer Count 2 Register RBUFCNT2 Field DescriptionsReceive Buffer Count 3 Register RBUFCNT3 Transmit Cppi DMA State Word 0 TCPPIDMASTATEW0Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions TxqheadptrTransmit Cppi DMA State Word 1 TCPPIDMASTATEW1 Transmit Cppi DMA State Word 2 TCPPIDMASTATEW2Sopdescriptorptr Currdescriptorptr TruncatednoneopTransmit Cppi DMA State Word 3 TCPPIDMASTATEW3 Transmit Cppi DMA State Word 4 TCPPIDMASTATEW4Transmit Cppi DMA State Word 5 TCPPIDMASTATEW5 Transmit Cppi Completion Pointer TcppicompptrReceive Cppi DMA State Word 1 RCPPIDMASTATEW1 Receive Cppi DMA State Word 0 RCPPIDMASTATEW0Sopbufferoffset Receive Cppi DMA State Word 1 RCPPIDMASTATEW1 RxqheadptrReceive Cppi DMA State Word 2 RCPPIDMASTATEW2 Receive Cppi DMA State Word 3 RCPPIDMASTATEW3108 Receive Cppi DMA State Word 5 RCPPIDMASTATEW5 Receive Cppi DMA State Word 4 RCPPIDMASTATEW4Pktlength Receive Cppi DMA State Word 6 RCPPIDMASTATEW6 Receive Cppi Completion Pointer RcppicompptrSopbufferbytecnt CurrbufferbytecntPower Management Register Power Power Management Register Power Field DescriptionsReadback / Compare Mode Function Address Register FaddrInterrupt Register for Receive Endpoints 1 to 4 Intrrx Field DescriptionsEP4TX EP3TX EP2TX EP1TX EP0 EP4TXInterrupt Enable Register for Intrtx Intrtxe Interrupt Enable Register for Intrrx IntrrxeEP4RX EP3RX EP2RX EP1RX EP4RXInterrupt Enable Register for Intrrx Intrrxe Interrupt Register for Common USB Interrupts Intrusb Vbuserr Sessreq Discon Conn SOF Resetbabble Resume SuspendVbuserr Interrupt Enable Register for Intrusb Intrusbe Interrupt Enable Register for Intrusb IntrusbeFrame Number Register Frame Frame Number Register Frame Field DescriptionsFramenumber EpselRegister to Enable the USB 2.0 Test Modes Testmode ForcehostForcefs ForcehsMaxpayload Servsetupend SetupendFlushfifo ServrxpktrdyDatatogwren DatatogISO Mode Dmaen Frcdatatog Dmamode ClrdatatogControl Status Register for Host Transmit Endpoint Hosttxcsr 124 ISO Dmaen Disnyet Dmamode Control Status Register for Host Receive Endpoint Hostrxcsr DataerrnaktimeoutDmaen Disnyet Dmamode Datatogwren 127 Count 0 Register COUNT0 Receive Count Register RxcountCount 0 Register COUNT0 Field Descriptions Receive Count Register Rxcount Field DescriptionsType Register Host mode only HOSTTYPE0 Transmit Type Register Host mode only HosttxtypeType Register Host mode only HOSTTYPE0 Field Descriptions SpeedNAKLimit0 Register Host mode only HOSTNAKLIMIT0 Transmit Interval Register Host mode only HosttxintervalEP0NAKLIMIT PolintvlnaklimitReceive Interval Register Host mode only Hostrxinterval Receive Type Register Host mode only HostrxtypeSpeed Prot Rendpn Configuration Data Register Configdata Field Descriptions Configuration Data Register ConfigdataMprxe 133 Transmit and Receive Fifo Register for Endpoint 0 FIFO0 DataTransmit and Receive Fifo Register for Endpoint 2 FIFO2 Transmit and Receive Fifo Register for Endpoint 1 FIFO1Data Ffff Ffff Transmit and Receive Fifo Register for Endpoint 3 FIFO3 Transmit and Receive Fifo Register for Endpoint 4 FIFO4OTG Device Control Register Devctl OTG Device Control Register Devctl Field DescriptionsBdevice Fsdev Lsdev Vbus Hostmode Hostreq Session BdeviceTransmit Endpoint Fifo Size Txfifosz Receive Endpoint Fifo Size RxfifoszTransmit Endpoint Fifo Size Txfifosz Field Descriptions Receive Endpoint Fifo Size Rxfifosz Field DescriptionsTransmit Endpoint Fifo Address Txfifoaddr Receive Endpoint Fifo Address RxfifoaddrReceive Endpoint Fifo Address Rxfifoaddr Field Descriptions AddrTransmit Hub Address Txhubaddr Transmit Function Address TxfuncaddrTransmit Hub Port Txhubport Receive Hub Address Rxhubaddr Receive Function Address RxfuncaddrReceive Hub Port Rxhubport 142 Table A-1. Document Revision History Additions/Modifications/DeletionsDSP Products ApplicationsRfid