AV8 Phase Locked Loop Board
Introduction
Refer To Block Diagram
The phase locked loop performs a comparison between the
incoming master clock from the crystal semiconductors
SPDIF receiver chip CS8415A and a locally derived
master clock from an xtal based Voltage controlled
oscilla tor (VCXO).
The comparison is made at Fs (44.1 or 48 KHz) rather than
the master clock frequency (256xFs) as this improves the
low frequency noise rejection of the circuit. The micro
cont roller on th e main digita l PCB (L8 96) kn ows what th e
incoming frequency is and can select the appropriate Xtal
oscillator using the control lines XTAL11.2896 and XTAL
12.288.
The phase comparison is used to dump or source current
from an integrating circuit which filters the pulses and
converts the charge to a voltage to control the VCXO.
When charge is dumped onto the integrator the voltage
decreases (as it inverts) and this in turn reduces the reverse
bias across the voltage control capacitor (Varicap).
Reducing the reverse bias makes the depletion region in
the diode become smaller increasing the capacitance.
Increasing the capacitance increases the load capacitance
on the xtal oscillator and thus reduces the frequency at
which the crystal oscillates. (The circuit works in the
opposite manner if charge is sourced off of the integrator)
This is the method by which frequency lock is achieved.
The phase of the circuit is arbitrary as it uses two dividers
that generate th e Fs s ignals.
The bypass circuit feeds the clock from the CS8415A
direct to the rest of the circuits in the event of any of the
following conditions.
! Phase locked loop cannot lock to the incoming
signal (i.e. it is not at Fs = 44.1 or 48KHz)
! To muc h jit ter on th e signa l that it goes ou ts ide
the +/- 150PPM tolerance
! When the loop is actively locking onto s ignal
In th e event that the ci rcuit is knock ed out of lock f or any
reason more than three times after the DSPs on the main
board have been reset it defaults to staying in bypass. This
is to prevent the situation where the master clock is
repeatedly lost.
Description
Refer to circuit diagram L948 sheet 1
The master clock from the digital PCB L896 comes in on
pin 2 of SK3 goes to both the divider IC1 and to the
bypass circuit IC6. The divider divides by 256 and the
clock at Fs then goes to the Comp input of the Phase
comparator IC4.
As the integrator inverts the polarity of the control voltage
the inputs on the Phase comparator are swapped over so
that the comparison input is used for the main signal and
the signal input is used for the comparison input. This
corrects the polarity of the complete control loop.
The sig input on the phase comparator is fed from the
second divider IC2. IC2 divides the output of the voltage
controlled xtal oscillator by 256 so that it is also at Fs.
The phase compar ator output PC 2 generates a cha r ge pulse
if the two signals are not exactly in phase and this pulse is
filtered and integrated by the opamp circuit IC5. IC5 runs
from +/- 1 2V rai ls so that the con trol volt age ra nge can be
increased from 5V at the ou tput of the phase comparator to
approximately 20V (+/- 10v) at the output of the opamp.
The increase voltage range allows a much greater
capacitance range to be achieved on the varicaps D1 and
D2. IC5 pin 3 is biased to 2.5 volts so that the 0 to 5V
input range can be converted to a positive and negative
output voltage.
IC5 Loop filter.
0V on the inpu t = 10V on th e output and 5 V on the in put
= -10V on the output
The DC control voltage from the output of IC5 pin 6 is fed
to the input of the varicaps D1 and D2. C31 and C35
provide an AC ground for the oscillator circuit.
R10,R11,C33,C40 and R12,R13,C38,C41 create a filtered
negative 12V bias for the diode so that a maximum
voltage of 22V (12V +10V) from opamp and a minimum
of 2V (12V –10V) can be present on the varicap.
The oscillator is a collpits type, the gain is provided by the
RF transistor Q1 and Q2. The oscillator can be turned on
and off by the digital transistors Q3 and Q5 this removes
the load from the emitter of the RF transistors. The output
of th e osc i llat or is via th e ca pa ci tor s C50 and C51 a fter t h e
capa citors th e signal i s bias ed to the th reshold p oint of th e
following gates IC3A and IC3C. The gates amplify the
signal then the signal is fed back to the input of the loop to
the di vider IC IC2 and t o the inpu t of a second buffer. Th e
second buffer is so that the micro can switch between the
original clock and the phase locked clock buffer. This is
achieved by IC3B and IC3D and the output (phase locked
or bypass) is fed back to the main digital PCB L896.
Q4 in the bypass feed is used to mute the input to IC3D
when the circuit is phased locked. This is to reduce any
cross talk from the original input master clock and the de-
ji ttered phase locked master clock.
Lock detection is performed using the PC1/PCP out
(PIN2) of IC4 the phase comparator. This signal goes low
whenever there is any phase error between the two
incoming signals so it can be used to determine if the
signal is in lock. When the signal is in lock this is always
high or has very small variations only due to tiny phase
error corrections. If the signals go out of lock the signal
goes low and the capacitor C12 is discharged fast via the
diode D3, to charge the cap up again the signal has to pass
through the resistor R15 so the circuit is biased towards
indic ation out of lock very qu ickly a nd on ly showing loc k
when the signal has been high for some time. As the
output of the PCP is a 5V signal and the Schmitt trigger
IC7 is a 3.3V part a potential divider is used to reduce this
voltage to a maximum of 2.5V by R15 and R25. The
Schmitt trigger cleans up the edge of this lock detection
signal and buffers it to be fed back to th e mic ro controller.
When the micro detects a lock signal it waits a further 3
seconds to make sure the lock is stable then checks the
lock signal again before switching from the bypass circuit
to th e phase locked cloc k.
Specification
Range
Lock range 44.1 KHz 11.2896 MH z +/-
150PPM
Lock r ang e 48 KHz 12. 288M H z +/-
150PPM