Arcam AV8 SPDIF Refer to circuit diagram L896 Sheet 8 , Microprocessor Refer to circuit diagram L896 Sheet 9

The signa l arrives at the f irst DSP either on the SPD IF I2 S
DATA line from the digital inpu ts or on ADC DATA 3.3V for
analogue inputs. The SPDIF chip generates the clocks for its
interfac es, and the ma ster clocks as it is th e system master . The
ADC generates its own bit clock and word clock from the
mas ter clock it receives from the ADC. When the ADC is in use
the master cloc k is generated by an 11.2896MHz cryst al
attached to the SPDIF receiver (IC803).
The audio da ta is passed between the two DSPS in a time
domain multi plexed form on the DSP_AUD0 line. The c locks
for this line are on DSP1_SCLK and DSP1_LRCLK. As six
channels are passed b et ween the two DSPS the interfaces works
at 3 x the normal I2S speed. ( 3x stereo cha n nels equal to six
channels).
Audio data passes out of the second DSP IC IC702 to the four
DAC’s via the serial terminators on pins 41 40 39 and 3. At this
point the audio data is in I2S format. The DSP generates clocks
for this audio data on pins 43 and 42 these are re-cl ocked and
buffered by IC1102 and IC1100.
A system c lock is passed to the DSP via pin30. This clock is
multipli ed inside the D SP chip using a phas e locked loop. The
pha se locked loop filter (PLL) is ma de up of the components on
pins 33 and 32. A smoothed supply is provided for the PLL via
the ferrites L701 and L700.
Cont rol of the DSPs from the micro-controller is via an SPI
(serial peripheral interface) and uses pins 6,7,18,19,20. SPI is a
Serial interface with clock (pin 7) and chip select (pin 18) in this
implementation the read (pin 6) and write (pin19) lines are
independe nt and pin 20 is the in terrupt line.
Chips IC704 to IC708 are the SRAM and SRAM interface.
IC70 4 is a level shifter from t he 2.5V out of the DSP’s to the
3.3V of the SRAM The components IC705 IC706 IC707 are
th e address latch . The address fr o m the 8 b it por t on the D S P is
latc hed through these three chips to form a 19 bit add ress for the
SRAM chip. IC708 is the SRAM chip. The SRAM interface is
used to provide the lip-sync function within the DSP.
SPDIF
Refer to circuit diagram L896 Sheet 8
The SPDIF receiver decodes the in coming SPDIF data into an
I2S stream a nd extracts the c locks f r om the signal.
The SPDIF signal arri ves at the input th rough the coupling cap
C824. The SPDIF sign al is BIPHASE dec oded to extract the
data and a PLL is synchronised to the left right preamble to
generate the system clock s. In th e absence of an input sign al the
chip switches over to the crystal oscillator on pin 21 this
assumes that the input is now coming from the ADC. In this
situation the only clock generated is the master clock, which is
used by the ADC to generate the clocks for its I2S interface and
by the DSPs t o generate clocks at their output s. If the system is
in Stereo bypass mode (i.e. pure stereo operation) OMCLK
STOP is used to shut down the crystal oscillator to reduce noise
in the box.
The phase locked loop filter is made up of C820, C821 and
R820. Th e supply for the PLL comes from P5VD via the local
inductor to give a local smooth supply.
The SPDIF chip is controlled via an SPI interface on pins
1,28,27,2,19. Data is received on pin 27 CDIN, transmitted on
pin 1 CDOUT, the clock is on pi n 28 CCLK, Chip select is on
Pin 2 and t he inter r upt line is on pi n 1 9.
SPDIS EMPH indicates weather the incoming signal has
emphasis or not. (Low = emphasis)
SPD IF RST Thi s is the res et signal, at power up it is held low to
keep the devi ce in reset until the power is stable.
IC802 is the master clock buffer and fans out the master clock to
th e other chips inside the product. Each line is series term inated
to redu ce reflection s on the line.
Microprocessor
Refer to circuit diagram L896 Sheet 9
This sheet contains the circuits for the H8S micro-controller.
The micro-controller has cont rol of all the system functions via
its I/O ports.
UARTS
The R S 232 po r t is connected to one (TXD1 R X D 1) of th e three
UART interfac es t he other two are used for the serial VFD
display updates (TXD0, SCK0) and the control of the DSP chips
(TXD2, RXD2 , SC LK2).
RS232 input is buffered via IC902, which generates and
receives th e le vels required for RS232 communication (+/- 12V)
INTERUPTS
Pins 33,34,37,38 are used as interrupts to the micro-controller.
Pin 33 is the SPDIF interrupt, Pins 34 and 37 are the interrupts
from the two DSP chi ps and 38 is the power fail interrupt.
RESET
The chip reset is formed usin g the Schmitt trigger inverters in
IC907 and the RC delay formed of C936 and R921. This is used
to latch the information on the program button through the d-
type flip-flop IC908A. The reset is fu rther delayed by the RC
C903 R916 then used to r elease the reset on th e Micro-
cont roller. This is so tha t the micro-controller mode (Program or
normal run) is set up before the reset is released on the micro.
DSP Clock
The clock for the DSP is generat ed from the Micro-controller
clock and is output on PF7/0.
This output i s a t 24.576MHz. The 24.567MHz clock is d ivided
by two by the D type Flip Flop IC908B. A 74LV74 is required
to p r ovide sufficient s peed to generate a 12.288M H z si gnal to
the DSPs. This output is under micro-controller control and is
shut off when the DSPs are not being used. (I.e. stereo bypass
mode and standby).
Static Po rt expanders
IC904 and 905 provide static control lines for the noise sensitive
pa r ts of the circuit, th e D ACs and ADC. They are serial
programmed via a bit bashed SPI type interface. Q900 generates
a output enab le low signal from the reset si gnal.
Buffers
IC900 is a level shifting buffer between 5V signals and the 3.3V
tolerant inpu ts on the micro.
EEPROM
A 8k EEPROM is used to store the configuration information
this is IC906 it is addressed using a bit bashed I2C interface.
Connectors
The t hree main con trol connect o r s are a lso on this sheet and
connect to the video SK900 audio SK902 and front panel SK
901 PCBs.