Texas Instruments SPRAA56 appendix Expected Values for the STS Objects

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SPRAA56

Figure 7. Statistics View Showing Benchmark Measurements

Look at both the average values and the maximum values to see how the application benchmarks are performing.

Note that STS objects hold 32-bit values on the target DSP. The values accumulated on the host PC are 64-bit values. The values on the target DSP are reset to zero when the host PC polls them for data. So, it is possible for the total value to overflow and restart at zero if you choose a slow update rate for the Statistics View in CCStudio. The maximum value is still accurate even if the total overflows. The average value is calculated on the host PC, and is not stored in the STS objects on the target DSP.

5.3.1 Expected Values for the STS Objects

Table 1 shows expected and measured values for the STS benchmarks in the instrumented application. The right column is blank in case you want to fill in your own measurements.

stsInVidPeriod, stsOutVidPeriod, and stsProcPeriod are all expected to be 33.33 ms, because this is the amount of time between successive frames in an NTSC video system.

The stsInVidTotal, stsOutVidTotal, and stsProcTotal values are expected to be slightly more than the sum of the Cell functions in each task, because the API calls are placed around a larger block than just the algorithm execution calls. The total values do not include time waiting on blocking calls like FVID_exchange or SCOM_getMsg, however.

The waiting time for the input and output tasks (stsInVidWait0 and stsOutVidWait0) are expected to be some value less than 33 ms, with a longer waiting time for the display than for the input.

DSP/BIOS Real-Time Analysis (RTA) and Debugging Applied to a Video Application

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Contents References Appendix A. Performance Impact Modifications to the Base ExampleRTA Techniques for Performance Measurement Viewing Benchmarks in the Instrumented ApplicationFigures Important Benchmarks for Video ApplicationsSPRAA56 Base Application OverviewTskInput 1 LOG DSP/BIOS and RF5 Components Used4 UTL 2 STS3 TRC Requirements for Viewing RTA Benchmarks Modifications to the Base ExampleAdding the Control TSK and MBX Communication Splitting the Encode and Decode CELLsTskO utput Querying the H.263 Encoder for StatusTskInput Controlling the Frame Rate Measuring Function Execution Time with the UTL Module RTA Techniques for Performance MeasurementMeasuring End-to-End Latencies Measuring Task Scheduling LatenciesMeasuring the Frame Rate Programmatic Measurement of Total CPU Load Memory Bus Utilization External memory 720*480 = 345,600 B86,400 B 14,400 BBitrate and Frame Type Methods for Transmitting Measured Performance Data Requirements Viewing Benchmarks in the Instrumented ApplicationApplication-Specific Control via GEL Scripts in CCStudio Load the h263loopbackrta.out program Running the ApplicationSPRAA56 Interpreting the Benchmarks Expected Values for the STS Objects Expected and Measured STS Benchmarks Expected and Measured Logged Benchmarks Debug ModeExpected Values Delivered to the Message Log Controlling the Run-Time Parameters DynamicallyCapture and Display Task Benchmarking ReferencesMeasured Performance of Benchmarking Techniques Appendix A. Performance ImpactOverhead of Performance Measurement Techniques RTA Effects on CPU LoadMemory Footprint Details Memory FootprintImportant Notice
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