Texas Instruments TPS54810 warranty PCB Layout

Page 10

TPS54810

www.ti.com

SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005

COMPENSA TION

NETWORK

BOOT

CAPACITOR

VOUT

PH

OUTPUT INDUCTOR

OUTPUT

FILTER

CAPACITOR

ANALOG GROUND TRACE

AGND

 

 

 

 

RT

VSENSE

 

 

SYNC

COMP

 

SS/ENA

PWRGD

 

 

VBIAS

 

 

 

 

 

 

BOOT

 

 

 

 

VIN

PH

 

EXPOSED

 

 

VIN

 

POWERP AD

 

 

 

 

AREA

 

 

 

PH

 

 

 

 

VIN

PH

 

 

 

 

VIN

PH

 

 

 

 

VIN

PH

 

 

 

PGND

 

 

 

 

PGND

PH

 

 

PH

 

 

PGND

PH

 

 

PGND

PH

 

 

PGND

FREQUENCY SET RESISTOR

SLOW ST ART

CAPACITOR

BIAS CAP ACITOR

VIN

INPUT INPUT

BYPASS BULK

CAPACITOR FILTER

TOPSIDE GROUND AREA

VIAto Ground Plane

Figure 10. PCB Layout

10

Image 10
Contents Features Efficiency AT 700 HZRecommended Operating Conditions Ordering InformationAbsolute Maximum Ratings Dissipation RATINGS1Electrical Characteristics Power Good Parameter Test Conditions MIN TYP MAX Unit Error AmplifierSLOW-START/ENABLE Output Power MosfetsPWP Package TOP View Terminal Name no DescriptionFunctional Block Diagram Related DC/DC ProductsInternal SLOW-START Time Junction Temperature Typical CharacteristicsOutput Voltage Regulation Error Amplifier Open Loop ResponseFeedback Circuit Application InformationComponent Selection Input Filter Operating FrequencyPCB Layout PCB Layout Recommended Land Pattern for the 28−Pin PWP PowerPAD Layout Considerations for Thermal PerformancePerformance Graphs from Application Circuit Shown in Figure Detailed Description Switching FRE Sync PIN RT PINQuency PWM Control Package Option Addendum Packaging InformationSPQ Tape and Reel InformationTPS54810PWPR Htssop Device Package Type Page Page Page Important Notice