Texas Instruments TPS54810 warranty Functional Block Diagram, Related DC/DC Products

Page 6

TPS54810

www.ti.com

SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005

FUNCTIONAL BLOCK DIAGRAM

AGND

VBIAS

 

VIN

 

 

 

 

 

 

 

 

 

 

 

 

 

Enable

 

 

 

 

 

 

 

 

 

 

SS/ENA

 

Comparator

 

 

 

 

 

 

VBIAS

REG

 

 

 

 

Falling

 

 

SHUTDOWN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Edge

 

 

 

 

 

 

 

 

1.2 V

 

 

 

 

 

ILIM

VIN

3 − 6 V

 

 

Deglitch

Thermal

 

 

 

Comparator

 

 

 

 

 

 

 

 

 

 

Hysteresis: 0.03 V

 

 

 

Leading

 

 

 

 

 

2.5

s

Shutdown

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

150°C

 

Edge

 

 

 

 

 

 

 

VIN UVLO

 

 

 

 

Blanking

 

 

 

 

 

 

 

Comparator

 

Falling

 

 

100 ns

 

 

 

 

 

 

 

 

 

and

 

 

 

 

 

 

 

 

 

VIN

 

 

 

 

 

 

BOOT

 

 

 

 

 

Rising

 

 

 

 

 

 

 

 

 

3.8 V

 

 

 

 

 

 

 

 

 

 

 

 

Edge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hysteresis: 0.16 V

Deglitch

 

 

 

 

 

30 m

 

 

 

 

 

 

2.5 s

 

SS_DIS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SHUTDOWN

 

LOUT

 

 

 

 

 

 

 

 

 

 

 

PH

VO

 

 

Internal/External

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Slow-Start

 

 

+

 

R

Q

Adaptive Dead-Time

 

CO

 

 

(Internal Slow-Start Time = 3.35 ms)

 

 

 

 

 

 

 

and

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

Error

 

 

Control Logic

 

 

 

 

 

 

 

 

PWM

 

 

 

 

 

 

 

 

 

 

Amplifier

 

 

 

 

 

 

 

 

Reference

 

Comparator

 

 

VIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VREF = 0.891 V

 

 

 

 

 

 

30 m

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OSC

 

 

 

PGND

 

 

 

 

 

Powergood

 

 

 

 

 

Comparator

 

 

 

 

 

VSENSE

 

PWRGD

 

 

 

 

Falling

 

 

 

 

 

 

 

 

0.90 Vref

 

Edge

TPS54810

 

 

Hysteresis: 0.03 Vref

SHUTDOWN

Deglitch

 

 

 

 

 

 

 

 

35 s

 

 

 

 

 

VSENSE

COMP

RT

SYNC

 

 

RELATED DC/DC PRODUCTS

DTPS56300—dc/dc controller

DPT6600 series—9-A plugin modules

6

Image 6
Contents Features Efficiency AT 700 HZRecommended Operating Conditions Ordering InformationAbsolute Maximum Ratings Dissipation RATINGS1Electrical Characteristics Power Good Parameter Test Conditions MIN TYP MAX Unit Error AmplifierSLOW-START/ENABLE Output Power MosfetsPWP Package TOP View Terminal Name no DescriptionFunctional Block Diagram Related DC/DC ProductsInternal SLOW-START Time Junction Temperature Typical CharacteristicsOutput Voltage Regulation Error Amplifier Open Loop ResponseFeedback Circuit Application InformationComponent Selection Input Filter Operating FrequencyPCB Layout PCB Layout Recommended Land Pattern for the 28−Pin PWP PowerPAD Layout Considerations for Thermal PerformancePerformance Graphs from Application Circuit Shown in Figure Switching FRE Sync PIN RT PIN Detailed DescriptionQuency PWM Control Package Option Addendum Packaging InformationTape and Reel Information SPQTPS54810PWPR Htssop Device Package Type Page Page Page Important Notice