Texas Instruments TPS54810 warranty Layout Considerations for Thermal Performance

Page 11

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TPS54810

SLVS420B − MARCH 2002 − R EVISED FEBRUARY 2005

LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE

For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and

any area available should be used when 8 A or greater operation is desired. Connection from the exposes area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Eight vias should be in the PowerPAD area with four additional vias located under the device package. The size of the vias under the package, but not in the exposed thermal pad area, can be increased to 0.018. Additional vias beyond the twelve recommended that enhance thermal performance should be included in areas not under the device package.

 

 

 

Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside

 

8 PL Ø0.0130

Powerpad Area 4 x 0.018 Diameter Under Device as Shown.

 

4 PL

Ø0.0180

Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground

 

Area Is Extended.

 

Connect Pin 1 to Analog Ground Plane

 

 

in This Area for Optimum Performance

0.06 0.0150

 

 

 

 

 

0.0339

 

 

 

 

0.0650

 

 

 

 

0.0500

 

 

0.3820

0.3478

0.0500

 

0.2090

 

 

0.0500

0.0256

 

 

 

 

 

 

 

0.0650

 

 

 

 

0.0339

 

Minimum Recommended Exposed

 

 

 

 

 

 

 

0.1700

Copper Area for Powerpad. 5-mil

 

 

 

Stencils May Require 10 Percent

 

 

 

 

Minimum Recommended Top

0.1340

Larger Area

0.0630

 

Side Analog Ground Area

 

 

 

 

0.0400

 

Figure 11. Recommended Land Pattern for the 28−Pin PWP PowerPAD

11

Image 11
Contents Efficiency AT 700 HZ FeaturesDissipation RATINGS1 Ordering InformationAbsolute Maximum Ratings Recommended Operating ConditionsElectrical Characteristics Output Power Mosfets Parameter Test Conditions MIN TYP MAX Unit Error AmplifierSLOW-START/ENABLE Power GoodTerminal Name no Description PWP Package TOP ViewRelated DC/DC Products Functional Block DiagramOpen Loop Response Typical CharacteristicsOutput Voltage Regulation Error Amplifier Internal SLOW-START Time Junction TemperatureOperating Frequency Application InformationComponent Selection Input Filter Feedback CircuitPCB Layout PCB Layout Layout Considerations for Thermal Performance Recommended Land Pattern for the 28−Pin PWP PowerPADPerformance Graphs from Application Circuit Shown in Figure Quency Switching FRE Sync PIN RT PINDetailed Description PWM Control Packaging Information Package Option AddendumTPS54810PWPR Htssop Tape and Reel InformationSPQ Device Package Type Page Page Page Important Notice