SCPA033
11.2Configuration Register Changes
•The device ID for the PCI1520 is AC55.
•Bit 23 in the System Control register (PCI offset 80h) is reserved on the PCI1520. On the PCI1420, this enabled PCI Bus power management specification revision 1.1 reporting. The PCI1520 is compliant to revision 1.1 by default.
•The default value of the Multifunction Routing register (PCI offset 8Ch) has been changed from 00000000h on the PCI1420 to 00001000h in order to enable IRQSER on MFUNC3 by default.
•Bit 6 in the Diagnostic register (PCI offset 93h) is reserved on the PCI1520 instead of AOSPMEN. The AOSPMEN feature of disabling oscillator power management is no longer necessary.
•Bit 0 in the Diagnostic register (PCI offset 93h) is no longer Asynchronous Interrupt Enable. The functionality is no longer necessary. It is now STDZVEN which enables the new ZV register model.
•Bits
•Bit 4 (AUX_PWR) in the Power Management Capabilities register (PCI offset A2h) is now tied to bit 15 (PME#_Support for D3Cold).
•D3_STAT# functionality has been added to MFUNC5, MFUNC4, and MFUNC2.
D3_STAT# is asserted when PME# is enabled and both functions are placed in D3 power state.
•Bit 27 in the Socket Present State register (Socket offset 08h) now indicates Zoom Video Support in that socket for the PCI1520. It is reserved in the PCI1420.
•Bit 27 in the Socket Force Event register (Socket offset 0Ch) now causes the ZVSUPPORT bit mentioned above to be set in the PCI1520. It is reserved in the PCI1420.
•Bits
•Registers and bits previously referring to centralized or distributed DMA are now reserved (bits
•The EEPROM loading map has changed significantly to provide more control for applications needing an EEPROM (see datasheet for details).
•Two registers have been added to the PME# context list (ExCA Power Control register and ExCA Interrupt and General Control register).
18 | PCI1520 Implementation Guide |