Texas Instruments PCI1520 manual PCI Bus Interface

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SCPA033

4 PCI Bus Interface

The PCI1520 has a 33MHz, 32 bit PCI Interface compliant with PCI Local Bus Specification Revision 2.2.

•PCLK, AD31:0, C/BE#3:0, PAR, DEVSEL#, FRAME#, STOP#, TRDY#, IRDY#, GNT#, and REQ# are required PCI signals. All except PCLK, GNT#, and REQ# are bussed signals. PCLK is a 33MHz point-to-point clock. GNT# and REQ# are point-to-point signals form the PCI bus arbitrator.

•PERR#, SERR#, and LOCK# are optional PCI signals. PERR# and SERR# are bussed signals and should be pulled up to VCC if unused. LOCK# is available on a Multifunction Terminal. If LOCK# is not needed for system implementation, it should not be configured as such in the Multifunction Routing register (PCI configuration offset 8Ch).

•GRST# (Global reset) and PRST# (PCI reset) are both used to initialize the PCI1520. The assertion of GRST# puts the PCI1520 in its default state. The assertion of PRST# does not initialize GRST# only bits. PRST# also does not initialize PME# context bits if PME# in enabled. More information can be found in Section 9.1 – D3 Wake Information.

•IDSEL should be resistively coupled (100Ω ) to one of the address lines between AD31 and AD11. Please refer to Section 3.2.2.3.5 (System Generation of IDSEL) and Section 4.2.6, footnote 31 (Pinout Recommendation) of the PCI Local Bus Specification Revision 2.2 for more information.

•PCI Interrupts can be routed through INTA# and INTB# through the Multifunction terminals. More information can be found in Section 7 – Interrupt Configurations.

•PCI CLKRUN# can be routed through Multifunction terminal 6. For more information, please refer to Section 9 – Power Management Considerations.

•PME# is used to signal Power Management Events. This signal is important for waking the PCI1520 from low power states. PME# is an open-drain signal.

•Pullup resistors are needed on the following PCI terminals: IRDY#, TRDY#, FRAME#, STOP#, DEVSEL#, PERR#, SERR#, LOCK#, PRST#, GRST#, INTA#, INTB#, CLKRUN#, and PME#.

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PCI1520 Implementation Guide

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Contents PCI1520 Implementation Guide Document History PCI1520 Typical System Implementation CardBus Controller Block System SideClamping Rails Power ConsiderationsInternal Voltage Regulator Bypass CapacitorsPower Switch Implementation Power Switch ImplementationPCI Bus Interface PC Card Interface Miscellaneous Pin Interface Multifunction TerminalsParallel IRQ and Parallel PCI Interrupts Interrupt ConfigurationsParallel PCI Interrupts Only Serial IRQ and Parallel PCI InterruptsEeprom Configuration Software ConsiderationsBios Considerations MFUNC5=GPI4, MFUNC4=SCLPCI Configuration Registers TI Extension Power Management Considerations D3 Wake InformationGRST# Only Registers PME#/RIOUT# Behavior CLKRUN# ProtocolPin Compatibility with Other Devices Migration to the PCI1520 from the PCI1420 Hardware and Pin Assignment ChangesConfiguration Register Changes Other Functional Differences Migration to the PCI1420 from the PCI1225 Configuration Register Changes Reference Schematics U2AWAIT# Ready INPACK# Reset References Important Notice
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