AMD manual GeodeLink Architecture3, AMD Geode, GX Processor, CS5535 Companion Device

Page 13

GeodeLink™ Architecture	32430C

GeodeLink™ Architecture3

GeodeLink™ architecture connects the internal modules of the AMD Geode™ GX processor using the data channels pro- vided by GeodeLink Interface Units (GLIUs). GeodeLink modules are connected to GLIU ports 1 – 7 as shown in Figure 3-

1.Port 0 is always the GLIU itself. GLIUs can be chained together and up to a maximum of six GLIUs can be connected allowing for 32 modules.

			GLMC
			GLMC
		1			CPU Core
		1			CPU Core
		0			3
					3
Not Used	7		GLIU0		4	DC







	6				5




	VP			2	GP


AMD Geode™		GLIU0		GLIU1							ACC




GX Processor

		1			Not Used				USBC1			5		DD
		1			Not Used				USBC1			5		DD
		0			2		6						4



Not Used	7		GLIU1		3	GLCP		GLCP			GLIU				ATAC




													3
	6				5		7			0			3
													2

Not Used

GLPCI

GIO

AMD Geode™

USBC2

CS5535

Companion

Device

GLPCI

PCI Bus

Figure 3-1. GeodeLink™ Architecture Topology

AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide

Image 13

Contents Publication ID 32430C AprilTrademarks Advanced Micro Devices, Inc. All rights reservedContents Contents GeodeLink Architecture Topology List of FiguresList of Figures List of Tables List of Tables Introduction Overview1Assumption Example MSR Transaction Model Specific Registers2Load MSR specified by ECX into Edxeax Write the value in Edxeax to MSR specified by ECXModel Specific Registers AMD Geode GeodeLink Architecture3GX Processor CS5535 Companion DeviceDescriptors GeodeLink MSR AddressingAddressing Example Memory Descriptor TypesProcessor Initialization Set Clocks and ResetSysref Mdiv VdivMemory Controller Initialization Calculating Processor SpeedCPU Identification GeodeLink Modules Initialization Test Extended DramSize Memory Default Region Configuration Properties Bit Descriptions Descriptor Allocation Glpci RegionsDescriptor MSR Address Chipset ID AMD Geode CS5535 Companion Device InitializationSet ID Select Idsel Gliu InitializationIRQ Mapper Multi Function General Purpose Timers MFGPTsKeyboard Emulation Logic KEL 1+ System Management Bus SMBusAcpi Power Management LogicFlash Interface Other Legacy DD InitializationATA-5 / Hard Drive Initialization Diverse Device I/O LocationsUniversal Serial Bus USB 7 AC97 Audio Controller InitializationPCI Bus Initialization Virtual System Architecture InitializationGeodeLink Control Processor Initialization Allocate Processor Frame Buffer and VSA2 MemoryInitialize Graphics Subsystem Miscellaneous InitializationsMonochrome Support Dual Monitor Support32430C Clocking Implementation5Scratchpad Initialization Post CodesImplementation Setup Options6 32430C ROM Memory7MapVSA Frame Buffer Memory MappedVSA PCI GeodeROM Flow GX Processor/CS5535 Device VSA Table A-1. Revision History Document Revision HistoryRevision # Revisions / Comments Initial release