AMD CS5535 IRQ Mapper, Keyboard Emulation Logic KEL 1+, System Management Bus SMBus, Gpio and ICF

Page 21

Initialization

32430C

4.2.4.1IRQ Mapper

Location:

I/O 20-21 master Programmable Interrupt Controller (PIC), I/O A0-A1 slave PIC, I/O 4D0 edge/level

 

PIC shadow register at MSR Address 51400034h

Description:

Initialization:

The use of the IRQ Mapper LBAR is optional since it is always accessible via MSRs. The LBAR is for the Mask and Mapper (MM) and the extended PIC (XPIC).

The IRQ Mapper is a combination of a Mapper and Mask (MM), an XPIC, and two Legacy 8259 compat- ible PICs (LPIC).

At reset, the PIC subsystem comes up in legacy mode. VSA initializes the XPIC to generate ASMI from GPIOs. Devices on the XPIC are hard wired to Interrupt Groups (IG) in the MM and XPIC. The XPIC is hooked to the LPIC on interrupts [0:1], [3:15]. The rest (16:64) are hooked to ASMI.

The XPIC has several incoming sources. They are IRQ, LPC, Y, and Z sources. The Y sources include software, USB, RTC alarm, audio, power management, NAND Flash, SMB, KEL, and UARTs. The Z sources include eight MFGPTs and eight GPIOs. During PCI scan, GeodeROM allocates memory, I/O, and interrupts to the PCI devices. This includes the virtual devices emulated by VSA. VSA is responsible for the setup of the XPIC mapper for the devices it is virtualizing.

4.2.4.2Keyboard Emulation Logic (KEL) 1+ 2

Location: NA

Description: Used for A20 support as well as USB keyboard emulation.

Initialization: VSA technology.

4.2.4.3System Management Bus (SMBus)

Location: 6000h

Description: SMBus is an industry standard two-wire serial interface. The SMBus is essentially an ACCESS.bus and is the interface used to read the DRAM SPD.

Initialization: GeodeROM sets the LBAR with the desired location and the GPIOs for SMBus. The recommended address (SMBADDR) is 0EFh.

4.2.4.4GPIO and ICF

Location: 6100h

Description: There are 23 GPIOs in Working mode and 5 in Standby mode. The GPIO registers are such that there is no need to do read/modify/writes. GPIO registers associated with bit settings are 32 bits. Thus, 16 GPIO may be changed at once. These are organized into Low and High banks. The Low bank deals with GPIOs 0 through 15 while the High bank deals with GPIOs 16 through 31.

Be aware of specification update issue #113 in certain silicon revisions (as of this writing, see AMD Geode™ CS5535 Companion Device Specification Update Silicon Revision A3 (publication ID 31534)). After a suspend, writing the register can not be done atomically.

Initialization: VSA technology will set and use GPIOs connected with SMIs.

Many GPIOs are muxed with other signals and must be set up appropriately. There is a GPIO INT and Power Management Event (PME) Mapper that maps GPIOs to the PIC and power management sub- system.

4.2.4.5Multi Function General Purpose Timers (MFGPTs)

Location:

6200h

Description:

Timers are used by VSA mostly. The timers can set and be set by GPIOs. The timers can output to non-

 

maskable interrupts and cause an ASMI through the XPIC with interrupts.

Initialization:

VSA technology.

AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide

21

Page 20 Page 22
Image 21
Page 20 Page 22
Contents Publication ID 32430C AprilTrademarks Advanced Micro Devices, Inc. All rights reservedContents Contents GeodeLink Architecture Topology List of FiguresList of Figures List of Tables List of Tables Introduction Overview1Assumption Example MSR Transaction Model Specific Registers2Load MSR specified by ECX into Edxeax Write the value in Edxeax to MSR specified by ECXModel Specific Registers AMD Geode GeodeLink Architecture3GX Processor CS5535 Companion DeviceDescriptors GeodeLink MSR AddressingAddressing Example Memory Descriptor TypesProcessor Initialization Set Clocks and ResetSysref Mdiv VdivCalculating Processor Speed Memory Controller InitializationCPU Identification Test Extended Dram GeodeLink Modules InitializationSize Memory Default Region Configuration Properties Bit Descriptions Glpci Regions Descriptor AllocationDescriptor MSR Address Chipset ID AMD Geode CS5535 Companion Device InitializationSet ID Select Idsel Gliu InitializationIRQ Mapper Multi Function General Purpose Timers MFGPTsKeyboard Emulation Logic KEL 1+ System Management Bus SMBusAcpi Power Management LogicFlash Interface Other Legacy DD InitializationATA-5 / Hard Drive Initialization Diverse Device I/O LocationsUniversal Serial Bus USB 7 AC97 Audio Controller InitializationPCI Bus Initialization Virtual System Architecture InitializationGeodeLink Control Processor Initialization Allocate Processor Frame Buffer and VSA2 MemoryInitialize Graphics Subsystem Miscellaneous InitializationsMonochrome Support Dual Monitor Support32430C Clocking Implementation5Scratchpad Initialization Post CodesImplementation Setup Options6 32430C Memory7Map ROMVSA Memory Mapped Frame BufferVSA PCI GeodeROM Flow GX Processor/CS5535 Device VSA Table A-1. Revision History Document Revision HistoryRevision # Revisions / Comments Initial release
Top Page Image Contents