Initialization | 32430C |
4.1.3.1Size Memory
Entry Conditions:
4 GB descriptor in FS Core register.
Procedure:
For each DIMM:
•Set the following in the MC_CF07_DATA register MSR Address 20000018h):
—Module Banks per DIMM
–SPD byte 5: Number of DIMM Banks
—Banks per SDRAM device
–SPD byte 17: Number of Banks on SDRAM device
—DIMM size - Size = Density * Banks
–SPD byte 5: Number of DIMM Banks
–SPD byte 31: Module Bank Density
—Page size - Page size = 2^# Column Addresses
–SPD byte 4: Number of Column Addresses
•Set CAS Latency in MC_CF8F_DATA register (MSR Address 20000019h):
—SPD byte 18: CAS Latency
—Turn on the memory interface in MC_CFCLK_DBUG bit MASK_CKE[1:0] (MSR Address 2000001Dh[9:8]).
—Do 12 refreshes (CF07_PROG_DRAM) for the Memory Controller to synchronize.
—Set the refresh rate of the DIMM – SPD byte 12: Refresh Rate/Type.
—Load RDSYNC counter with sync value.
Note: See the AMD Geode™ GX Processors Data Book (publication ID 31505) for bit descriptions and allocation.
4.1.4Test Extended DRAM
Entry Conditions:
4 GB descriptor in FS Core register.
All memory configured.
Procedure:
•Set GLIU descriptor to allow writes to memory.
•Make sure interface is turned on in MC_CFCLK_DBUG bit MASK_CKE[1:0] (MSR Address 2000001Dh[9:8]).
•Determine total amount of memory by doing a read/write test.
•For each 1 MB block of memory:
1)Walk a 1 through data bus at first location of block.
2)Walk a 0 through data bus at first location of block.
3)Check for stuck address line in the block.
•Continue test if no memory present for debug purposes.
4.1.5GeodeLink™ Modules Initialization
Descriptors routing memory and I/O for GX processor modules are initialized by GeodeROM and Virtual System Architec- ture™ (VSA) technology. GeodeLink modules that are virtualized by VSA technology and use PCI memory or PCI I/O, report that resource in the virtual PCI header. The GLIU is configured with MSRs like all GX processor modules.
AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide | 17 |