AMD CS5535 manual Processor Initialization, Set Clocks and Reset, Sysref, Mdiv Vdiv

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Initialization

32430C

 

 

Initialization4

4.1Processor Initialization

The AMD Geode™ GX processor contains many of the components normally found in system support chipsets. GeodeROM must set up these components, including the DRAM controller, L1 cache controller, clock control, and PCI con- troller as well as some proprietary systems like GeodeLink™ architecture.

This chapter contains descriptions and some pseudo code for GX processor-specific code sequences in GeodeROM. The modifications are grouped into CPU core initialization, DRAM controller initialization, GeodeLink interface initialization, PCI bus initialization, and miscellaneous other initializations/changes.

4.1.1Set Clocks and Reset

Register: GLCP_SYS_RSTPLL (GX GLCP MSR Address 4C000014h)

The GX processor has separate clocks for the CPU core and GeodeLink interface. These clocks are derived from the sys- tem PLL, which is driven by the PCI clock. At power-on, these clocks default to a safe value. Setting the clock registers and doing a reset will re-clock the GX processor.

The clocks are controlled by three divisors as shown in Figure 4-1.The Feed-back Divisor (FbDIV) in the PLL sets sppl_raw_clk. Sppl_raw_clk is divided by the GeodeLink Divisor (MDIV) and the CPU Divisor (VDIV) to derive GeodeLink clock and CPU clock. Sppl_raw_clk must be between 300 MHz and 800 MHz. The GeodeLink clock is used to clock the memory. Therefore, the GeodeLink clock should never be greater than the speed and type of the system memory.

All the divisor bits, software bits, memory type bit, and reset bits are located in the GLCP_SYS_RSTPLL register. Once the divisors and memory type (DDR/SDR) are set, the BIOS sets a reset flag and resets the CPU to continue initialization at the desired CPU speed.

GeodeROM sets the clocks based on jumper settings that are interpreted to match SKUs defined for that version of the CPU. SKUs are defined by PCI speed, memory type (SDR or DDR), and the jumper setting. GeodeROM can also use FbDIV, MDIV, and VDIV values set by the user in CMOS for debugging.

If there is an incorrect setting in CMOS setup and the system cannot boot three times in a row, GeodeROM resets CMOS to the defaults.

See Figure 7-4 on page 33 for example reset and system clock logic.

GLIU Clock

SYSREF

(PCI Clock)

0 - 66 MHz

Clock

System PLL

300 - 800 MHz

Clock

FbDIV

spll_raw-clk

MDIV

VDIV

CPU Core Clock

Figure 4-1. Clock Control

AMD Geode™ GX Processor/CS5535 Companion Device GeodeROM Porting Guide

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Contents Publication ID 32430C AprilTrademarks Advanced Micro Devices, Inc. All rights reservedContents Contents GeodeLink Architecture Topology List of FiguresList of Figures List of Tables List of Tables Introduction Overview1Assumption Write the value in Edxeax to MSR specified by ECX Model Specific Registers2Example MSR Transaction Load MSR specified by ECX into EdxeaxModel Specific Registers CS5535 Companion Device GeodeLink Architecture3AMD Geode GX ProcessorMemory Descriptor Types GeodeLink MSR AddressingDescriptors Addressing ExampleMdiv Vdiv Set Clocks and ResetProcessor Initialization SysrefCalculating Processor Speed Memory Controller InitializationCPU Identification Test Extended Dram GeodeLink Modules InitializationSize Memory Default Region Configuration Properties Bit Descriptions Glpci Regions Descriptor AllocationDescriptor MSR Address Gliu Initialization AMD Geode CS5535 Companion Device InitializationChipset ID Set ID Select IdselSystem Management Bus SMBus Multi Function General Purpose Timers MFGPTsIRQ Mapper Keyboard Emulation Logic KEL 1+Other Legacy DD Initialization Power Management LogicAcpi Flash Interface7 AC97 Audio Controller Initialization Diverse Device I/O LocationsATA-5 / Hard Drive Initialization Universal Serial Bus USBAllocate Processor Frame Buffer and VSA2 Memory Virtual System Architecture InitializationPCI Bus Initialization GeodeLink Control Processor InitializationDual Monitor Support Miscellaneous InitializationsInitialize Graphics Subsystem Monochrome Support32430C Post Codes Implementation5Clocking Scratchpad InitializationImplementation Setup Options6 32430C Memory7Map ROMVSA Memory Mapped Frame BufferVSA PCI GeodeROM Flow GX Processor/CS5535 Device VSA Initial release Document Revision HistoryTable A-1. Revision History Revision # Revisions / Comments
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