5. Appendix
5.1 POST Code Definitions
5.1.1 AWARD POST Code Definitions
| POST |
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| Description |
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| (hex) |
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| CF |
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| Test CMOS R/W functionality |
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| Early chipset initialization: |
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| C0 |
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| Detect memory |
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| C1 |
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| C3 |
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| Expand compressed BIOS code to DRAM |
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| C5 |
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| Call chipset hook to copy BIOS back to E000 & F000 shadow RAM |
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| 01 |
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| Expand the Xgroup codes locating in physical address 1000:0 |
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| 03 |
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| Initial Superio_Early_Init switch |
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| 05 |
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| 1. Blank out screen |
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| 2. Clear CMOS error flag |
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| 07 |
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| 1. Clear 8042 interface |
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| 2. Initialize 8042 |
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| 08 |
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| 1. Test special keyboard controller for Winbond 977 series Super I/O chips |
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| 2. Enable keyboard interface |
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| 1. Disable PS/2 mouse interface (optional) |
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| 0A |
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| 2. Auto detect ports for keyboard & mouse followed by a port & interface swap (optional) |
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| 3. Reset keyboard for Winbond 977 series Super I/O chips |
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| 0E |
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| Test F000h segment shadow to see whether it is |
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| the speaker |
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| 10 |
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| Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for |
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| ESCD & DMI support |
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| 12 |
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| Use walking 1’s algorithm to check out interface in CMOS circuitry. Also set |
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| power status, and then check for override |
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| 14 |
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| Program chipset default values into chipset. Chipset default values are MODBINable by |
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| OEM customers |
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| 16 |
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| Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST |
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| 26. |
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| 18 |
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| Detect CPU information including brand, SMI type (Cyrix or Intel) and CPU level (586 or 686) |
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| 1B |
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| Initial interrupts vector table. If no special specified, all H/W interrupts are directed to |
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| SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR. |
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| 1D |
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| Initial EARLY_PM_INIT switch |
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| 1F |
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| Load keyboard matrix (notebook platform) |
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| 21 |
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| HPM initialization (notebook platform) |
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| 23 |
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| 1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute. |
| Appendix |
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| 2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead. |
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| 24 |
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| Prepare BIOS resource map for PCI & PnP use. If ESCD is valid, take into consideration of |
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| the ESCD’s legacy information. |
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AN9 32X |