Advantech AIMB-221 manual Connecting Peripherals

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The TFP410 is a DVI-compliant digital transmitter that is used in digital host monitor systems to T.M.D.S. encode and serialize RGB pixel data streams. TFP410 supports resolutions from VGA to UXGA and can be controlled in two ways:

1.Configuration and state pins or

2.The programmable I2C serial interface (see the terminal functions section).

The host in a digital display system, usually a PC or consumer electronics device, contains a DVI-compatible transmitter such as the TI TFP410 that receives 24-bit pixel data along with appropriate control signals. The TFP410 encodes the signals into a high speed, low voltage, differential serial bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a DVI compatible receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by dis- tances up to 5 meters or more, serial transmission of the pixel data is preferred (see the T.M.D.S. pixel data and control signal encoding, pixel data and control signal encoding, universal graphics control interface voltage signal levels, and universal graphics controller interface clock inputs sections).

The TFP410 integrates a high-speed digital interface, a T.M.D.S. encoder, and three differential T.M.D.S. drivers. Data is driven to the TFP410 encoder across 12 or 24 data lines, along with differential clock pair and sync signals. The flexibility of the TFP410 allows for multiple clock and data formats that enhance system perfor- mance.

The TFP410 also has enhanced PLL noise immunity, an enhancement accomplished with on-chip regulators and bypass capacitors.

The TFP410 is versatile and highly programmable to provide maximum flexibility for the user. An I2C host interface is provided to allow enhanced configurations in addi- tion to power-on default settings programmed by pin-strapping resistors.

Chapter 2 Connecting Peripherals

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AIMB-221 User Manual

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Contents AIMB-221 Message to the Customer Copyright AcknowledgementsDeclaration of Conformity AIMB-221 Memory Tested for Compatibility Memory CompatibilityProduct warranty Initial Inspection Contents Award Bios Setup Advanced Chipset Features screen Chipset Software Installation Utility VGA Setup71 Chapter Introduction FeaturesMemory SpecificationsSystem Industrial features Jumpers and ConnectorsMechanical and environmental specifications Input/OutputChapter Board Layout Jumper and Connector LocationsAMD M690E AIMB-221 Block DiagramLabel Function How to set jumpers Safety Precautions Jumper SettingsCmos clear JCMOS1 Watchdog timer output JWDT1ATX/AT mode selector JPSON1 Processor Installation Memory Installation ProceduresSystem Memory Cache MemoryID SEL PCI Bus Routing TableMINIPCI1 Routing AD28 / #INTE / #INTF PCI#IDSELAD28 Connecting Peripherals Primary IDE1 IDE Connector IDE1 Connecting PeripheralsPIN DVI2 OptionalConnecting Peripherals Front Panel Connectors JFP1, JFP2, JFP3 Reset Connector JFP1 ATX Soft Power Switch JFP1External Speaker JFP2 JFP1JFP2 HDD LED Connector JFP2SM Bus Connector JFP2 PIN6,8 JFP3 Power LED and keyboard lock connector JFP3JPSON1 ATX/AT Mode Selector JPSON1COM3 Serial Port Header COM 3/4/5/6COM4 COM5CPUFAN1 CPU Fan Connector CPU Fan1SYSFAN2 System Fan SYSFAN1, SYSFAN2SYSFAN1 Parallel Port LPT1 LPT1 JSETCOM1 JSETCOM2 JSETCOM2RS-422 GPIO1 GPIO1HDMI1 VGA1 VGA HdmiLAN1USB12 14 LAN1USB12LAN2USB34 15 LAN2USB34USB56 16 USB56USB78 17 USB78AUDIO1 AudioFPAUD1 FPAUD1SPKOUT1 SPKOUT1Serial ATA Interface SATA1, SATA2, SATA3, SATA4 SATA1 SATA2 SATA3 SATA4 SATA2INV1 22 INV1TVOUT1 23 VGA2 TV-Out OptionalRight click the grey TV icon and select the display mode Lvds LVDS1 JLVDS1 Lvds Power Jumper JLVDS1Page Award Bios Setup Bios Setup program Cmos RAM Auto-backup and Restore Entering SetupDate Standard Cmos SetupTime IDE channel 0/1 Master/SlaveHalt On Advanced Bios FeaturesVideo Hard Disk Boot Priority CPU FeaturesQuick Power On Self Test First/Second/Third Boot DeviceBoot Up NumLock Status Boot Up Floppy SeekTypematic Rate Setting Typematic Delay msecMemory Hole At 15M-16M Advanced Chipset FeaturesIntegrated Peripherals Dvmt ModeOn-Chip Frame Buffer Size Dvmt / Fixed Memory SizeIDE DMA Transfer Access IDE HDD Block ModeIDE Primary Master/Slave PIO/UDMA Mode Auto Sata ModeAward Bios Setup On board LAN1 ROM Legacy mode supportOnboard LAN2 Control On board LAN2 ROMPower Management Setup HDD Power Down Suspend ModePowerOn by LAN PowerOn by ModemPnP/PCI Configurations PC Health Status Spread Spectrum Frequency / Voltage ControlPlease Enter Your Password Password SettingExit Without Saving Save & Exit SetupPage Chipset Software Installation Utility VGA Setup Before you begin Chipset Software Installation Utility and VGA Setup Windows XP Driver Setup Chipset Software Installation Utility and VGA Setup Page Chipset Software Installation Utility and VGA Setup Page Chipset Software Installation Utility and VGA Setup Page LAN Configuration Win XP Driver Setup LAN InstallationLAN Configuration Click Finish to complete the installation AC97 Audio Setup Windows XP Driver Setup AC97 AC97 Audio Setup Page Appendix a Programming the Watchdog Timer Watchdog timer overviewReset/Interrupt selection Appendix a Programming the Watchdog Timer Example Programs Table A.1 Watchdog timer registersAppendix a Programming the Watchdog Timer Page Appendix a Programming the Watchdog Timer Page Appendix a Programming the Watchdog Timer