Advantech AIMB-250 user manual Ior#, Iow#, Iordy, Reset#, Dreq, Dack#, Dact#

User’s Manual

2.4.16.1Signal Description – Primary / Secondary IDE Connector (IDE_1, IDE_2) The IDE interface supports PIO modes 0 to 4 and Bus Master IDE. Data transfer rates up to 100 MB/Sec is possible.

Signal		Signal Description
DA [2:0]		IDE Address Bits. These address bits are used to access a register or data port in
		a device on the IDE bus.
DCS1#, DCS3#		IDE Chip Selects. The chip select signals are used to select the command block
		registers in an IDE device. DCS1# selects the primary hard disk.
D [15:0]		IDE Data Lines. D [15:0] transfers data to/from the IDE devices.
IOR#		IDE I/O Read. Signal is asserted on read accesses to the corresponding IDE port
		addresses.
IOW#		IDE I/O Write. Each signal is asserted on write accesses to corresponding the IDE
		port addresses.
IORDY		When deasserted, these signals extend the transfer cycle of any host register
		access when the device is not ready to respond to the data transfer request.
RESET#		IDE Reset. This signal resets all the devices that are attached to the IDE interface.
IRQ14	Interrupt line from hard disk. Connected directly to PC-AT bus.
DREQ		The DREQ is used to request a DMA transfer from the South Bridge. The direction
		of the transfers is determined by the IOR#/IOW# signals.
DACK#		DMA Acknowledge. The DACK# acknowledges the DREQ request to initiate DMA
		transfers.
DACT#		Signal from hard disk indicating hard disk activity. The signal level depends on the
		hard disk type, normally active low. The signal is routed directly to the LED1.
PATADET,		Primary/Secondary IDE detected.
SATADET

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