June 23, 2010 |
8.20.4.7 Offset 8 - DMA channel/Multiword DMA Type
If the BIOS has configured the system to perform multiword DMA data transfers in place of PIO transfers, this field shall specify the DMA mode in the upper four bits, as per the definition in
8.20.4.8 Offset 9 - PIO type
If the BIOS has configured the system to perform PIO data transfers other than mode 0, this field shall specify the PIO mode as per the definition in
8.20.4.9 Offset 10-11 - BIOS selected hardware specific option flags
These bytes specify the current hardware options enabled by the BIOS, a bit for each of the options listed below.
8.20.4.9.1 Bit 0 - fast PIO
If the system is configured for a PIO mode greater than 0, this bit shall be set to one and byte 9 (PIO Type) shall be used to configure the system. If this bit is cleared to zero, the
8.20.4.9.2 Bit 1 - fast DMA
If the system is configured for DMA, this bit shall be set to one and byte 8 (DMA Channel/DMA Type) should be used to configure the system. If this bit and bit 11, clause 8.24.3.9.11, are cleared to zero, then the DMA Channel/DMA Type field shall be ignored.
8.20.4.9.3 Bit 2 - ATA READ/WRITE MULTIPLE
If the system is configured for
8.20.4.9.4 Bit 3 - CHS translation
If the device reports more than 1024 cylinders in the IDENTIFY DEVICE command data, this bit shall be set to one. See 8.20.4.9.10 to determine the method of geometry translation.
8.20.4.9.5 Bit 4 - LBA translation
If the system is configured for LBA type addressing, this bit shall be set to one and the Extended INT 13h interface (FN 41h through 48h) shall pass LBA values directly to the device. The conventional INT 13h interface shall ignore this bit and shall use CHS.
8.20.4.9.6 Bit 5 - removable media
If the device supports removable media, this bit shall be set to one and the extended INT 13h device locking and ejecting subset shall also be supported.
8.20.4.9.7 Bit 6 - ATAPI device
If this ATA device implements the PACKET command feature set (ATAPI) as defined in
8.20.4.9.8 Bit 7 - 32-bit transfer mode
If the BIOS has configured the host adapter to perform
8.20.4.9.9 Bit 8 - ATAPI device uses command packet interrupt
If bit 6 is cleared to zero, then this field shall be ignored and shall be zero. If bit 6 is set to one, this bit indicates how the ATAPI devices signals it is ready to receive a packet command. When this bit is set to one, it indicates that the ATAPI device returns an interrupt, and sets DRQ, when it is ready for a packet. When this bit is cleared to zero, it indicates that the ATAPI device sets DRQ, without an interrupt, when it is ready for a packet.
56 | Working Draft Enhanced Disk Drive - 4 |