Feature |
| Option | Description | |
Memory Configuration |
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| Limit | Select the DRAM Frequency | |
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| programming method. If Auto, the | ||
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| DRAM speed will be based on | |
Memclock Mode |
| Auto | ||
| SPDs. If Limit, the DRAM speed will | |||
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| not exceed the specified value. If | |
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| Manual | Manual, the DRAM speed specified | |
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| will be programmed by users. | ||
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| 400 |
| |
Memory Clock Value | 533 | Set Memory Value | ||
667 | ||||
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| 800 |
| |
MCT Timing Mode |
| Manual | Allow user to configure the MCT | |
| Auto | Timing Mode manually. | ||
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CAS Latency (CL) |
| Auto | Set CAS Latency | |
| 3.0 ~ 6.0 | |||
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TRAS |
| Auto | Set TRAS | |
| 5CLK ~ 18CLK | |||
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TRP |
| Auto | Set TRP | |
| 3CLK ~ 6CLK | |||
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TRCD |
| Auto | Set TRCD | |
| 3CLK ~ 6CLK | |||
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TRRD |
| Auto | Set TRRD | |
| 2T ~ 5T | |||
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TRC |
| Auto | Set TRC | |
| 11T ~ 25T | |||
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Bank Interleaving |
| Disabled | Enable Bank Memory Interleaving | |
| Auto | |||
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Enable Clock to All DIMMs | Enabled | Enable unused clocks to DIMMs | ||
| even memory slots are not | |||
Disabled | ||||
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| populated. | ||
MemClk Tristate |
| Enabled | Enable/Disable MemClk | |
C3/ATLVID |
| Disabled | during C3 and Alt VID | |
CS Spuring Enable |
| Enabled | Reserve a spare memory rank in | |
| Disabled | each mode. | ||
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| Enabled | Turning this off will require custom | |
DQS Signal | Training | memory timings programming. | ||
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Control |
| Disabled | Training will be automatically | |
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| disabled if CS sparing is enabled. | ||
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Memory Hole Remapping | Enabled | Enable Memory Remapping around | ||
Disabled | Memory Hole | |||
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