External Clock | Omega Engineering DAQ-12 guide

When configured for a 48-bit divider, the first sampling period will be slightly longer than the others because the first clock period is required to load the initial value of the multi-function timer. The following equation calculates the additional time of the first period:

tadd = 100ns * [N1 * N2]

To minimize the amount of additional time required for the first sample, select clock dividers such that N1 and N2 are as small as possible and N3 is as large as possible. Using the equations above, the minimum and maximum data sampling rates and the amount of additional time required for the first sample can be calculated.

Maximum sampling rate:	Minimum sampling rate:
N1 = 2, N2 = 5, N3 = 5	N1 = 65535, N2 = 65535, N3 = 65535
t = 100 x 10−9 * [(2)(5)(5)]	t = 100 x 10−9 * [(65535)(65535)(65535)]
t = 100 x 10−9 * 50	t = 100 x 10−9 * [2.815 x 1014 ]
t = 5 us	t = 28.146 x 106 sec
	t = 325 days, 18 hours, 23 minutes, 29 sec
f = 10 x 106 / [(2)(5)(5)]
f = 10 x 106 / 50	f = 10 x 106 / [(65535)(65535)(65535 )]
f = 200 Khz	f = 10 x 106 / [2.815 x 1014 ]
	f = 35.529 nHz
tadd = 100 x 10−9 * [2 * 5]	tadd = 100 x 10−9 * [65535 * 65535]
tadd = 100 x 10−9 * 10	tadd = 100 x 10−9 * [4.295 x 109 ]
tadd = 1 us	tadd = 429.5 sec

2.5.2External Clock

The external clock input to the DAQ-12 is a TTL level (0 - 5 volt) signal. This input may be used to control the sampling rate directly, or it may be fed through a pre-divider (the multi-function timer) with the timer output controlling the A/D sampling rate. When used to control the sampling rate directly, the frequency of the external clock input may be varied from DC to 100 KHz as long as the width of the low and high portions of the clock are a minimum of 1 us each. The A/D conversion cycle will begin on each rising edge of the external clock input. (See Figure 2-7).

1 usec min

5 usec min

Figure 2-7. Sampling Rate External Clock Pulses

DAQ-12 Users Manual