Cypress CY24271, CY24272 manual Input and Output Waveforms, Crossing Point Voltage

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CY24272

Figure 4. Input and Output Waveforms

V H

80%

V (t)

20%

V L

tR

tF

Figure 5. Crossing Point Voltage

CLK

CLKB

Vx+

Vx.nom

Vx-

Figure 6. Cycle-to-cycle Jitter

CLK

CLKB

tCYCLE,i

 

 

 

tCYCLE,i+1

 

 

tJ = tCYCLE,i - tCYCLE,i+1 over 10,000 consecutive cycles

CLK

CLKB

Figure 7. Cycle-to-cycle Duty-cycle Error

 

tPW-(i)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPW+(i)

 

 

 

 

 

tPW-(i+1)

 

 

 

 

 

 

 

tPW+(i+1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYCLE,(i) tCYCLE,(i+1)

tDC,ERR = tPW-(i) - tPW-(i+1) and tPW-(i+1) - tPW+(i+1)

Document Number: 001-42414 Rev. **

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Contents PLL FeaturesLogic Block Diagram Device Comparison CY24271 CY24272Pin Definition 28 Pin Tssop Pin No Name Description PinoutsModes of Operation Input Clock SignalPLL Multiplier Bypass Device ID and SMBus Device AddressSMBus Protocol SMBus Data Byte DefinitionsPOD Command Code 80h5 Bit RegisterCommand Code 81h Bit Register Command Code 82h Bit RegisterParameter Description Condition Min Max Unit Absolute Maximum ConditionsRefclkb VTHDC Operating Conditions Parameter Description Min Typ Max Unit DC Electrical SpecificationsAC Operating Conditions AC Electrical Specification Parameter Value Unit Test and Measurement SetupSignal Waveforms JitterCrossing Point Voltage Input and Output WaveformsCY24272ZXCT Package Drawing and DimensionOrdering Information Part Number Package Type Product Flow Pb-FreeKVM/AESA Document HistoryREV ECN no