Cypress CY24272, CY24271 manual Absolute Maximum Conditions, Refclkb, Vth, Esdhbm

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CY24272

Figure 2. Differential and Single-Ended Clock Inputs

Supply Voltage

REFCLKB

Input

REFCLK

XDR Clock Generator

VTH

Input

REFCLK

XDR Clock Generator

Differential InputSingle-ended Input

Absolute Maximum Conditions

Parameter

Description

Condition

Min

Max

Unit

VDD

Clock Buffer Supply Voltage

 

–0.5

4.6

V

VDDC

Core Supply Voltage

 

–0.5

4.6

V

VDDP

PLL Supply Voltage

 

–0.5

4.6

V

VIN

Input Voltage (SCL and SDA)

Relative to VSS

–0.5

4.6

V

 

Input Voltage (REFCLK/REFCLKB)

Relative to VSS

–0.5

VDD + 1.0

V

 

Input Voltage

Relative to VSS

–0.5

VDD + 0.5

V

TS

Temperature, Storage

Non-functional

–65

150

°C

TA

Temperature, Operating Ambient

Functional

0

70

°C

TJ

Temperature, Junction

Functional

150

°C

ØJA

Junction to Ambient thermal resis-

Zero air flow

100

°C/W

 

tance

 

 

 

 

ESDHBM

ESD Protection (Human Body Model)

MIL-STD-883, Method 3015

2000

V

Document Number: 001-42414 Rev. **

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Contents Device Comparison CY24271 CY24272 FeaturesLogic Block Diagram PLLPinouts Pin Definition 28 Pin Tssop Pin No Name DescriptionInput Clock Signal PLL MultiplierModes of Operation SMBus Data Byte Definitions Device ID and SMBus Device AddressSMBus Protocol BypassCommand Code 82h Bit Register Command Code 80h5 Bit RegisterCommand Code 81h Bit Register PODVTH Absolute Maximum ConditionsRefclkb Parameter Description Condition Min Max UnitDC Operating Conditions DC Electrical Specifications AC Operating ConditionsParameter Description Min Typ Max Unit AC Electrical Specification Jitter Test and Measurement SetupSignal Waveforms Parameter Value UnitInput and Output Waveforms Crossing Point VoltagePart Number Package Type Product Flow Pb-Free Package Drawing and DimensionOrdering Information CY24272ZXCTDocument History REV ECN noKVM/AESA