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AC Electrical Specification |
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The AC Electrical specifications follow. [6] |
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Parameter |
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| Description | Min | Typ | Max |
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t | Clock Cycle time[19] | 1.25 |
| 3.34 |
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CYCLE |
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tJIT(cc) | Jitter over | – | 25 | 40 |
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| Jitter over | – | 25 | 30 |
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L20 | Phase noise SSB spectral purity L(f) at 20 MHz offset: | – |
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| (In addition, device must not exceed L(f) = 10log[1+(50x106/f)2.4] |
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| f = 1 MHz to 100 MHz except for the region near f = REFCLK/Q where Q is |
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| the value of the internal reference divider.) |
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tJIT(hper,cc) | – | 25 | 40 |
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| – | 25 | 30 |
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ΔtSKEW | Drift in tSKEW when ambient temperature varies between 0°C and 70°C and | – | – | 15 |
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| supply voltage varies between 2.375V and 2.625V.[21] |
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DC | Long term average output duty cycle | 45% | 50 | 55% |
| tCYCLE |
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tEER,SCC | PLL output phase error when tracking SSC | – | 100 |
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tCR,tCF | Output rise and fall times at | – | 150 | – |
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| voltage) |
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tCR,CF | Difference between output rise and fall times on the same pin of the single | – | – | 100 |
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Table 9. SMBus Timing Specification
Parameter | Description | Min | Max | Units |
FSMB | SMBus Operating Frequency | 10 | 100 | kHz |
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TBUF | Bus free time between Stop and Start Condition | 4.7 |
| μs |
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THD:STA | Hold time after (Repeated) Start Condition. | 4.0 |
| μs |
| After this period, the first clock is generated. |
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TSU:STA | Repeated Start Condition setup time | 4.7 |
| μs |
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TSU:STO | Stop Condition setup time | 4.0 |
| μs |
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THD:DAT | Data Hold time | 0 |
| ns |
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TSU:DAT | Data Setup time | 250 |
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TTIMEOUT | Detect clock low timeout |
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| Not supported |
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TLOW | Clock low period | 4.7 |
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THIGH | Clock high period | 4.0 | 50 | μs |
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TLOW:SEXT | Cumulative clock low extend time (slave device) |
| 25 | ms |
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| CY24272 doesn’t |
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| extend |
TLOW:MEXT | Cumulative clock low extend time (master device) |
| 10 | ms |
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TF | Clock/Data Fall Time |
| 300 | ns |
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TR | Clock/Data Rise Time |
| 1000 | ns |
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TPOR | Time in which a device must be operational after power on reset |
| 500 | ms |
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Document Number: | Page 9 of 13 |
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