Cypress CY62136VN manual Switching Characteristics Over the Operating Range, Write Cycle 12

CY62136VN MoBL®

Switching Characteristics Over the Operating Range [9]

						55 ns			70 ns
Parameter					Description						Unit
						Min.	Max.	Min.		Max.
Read Cycle
tRC	Read Cycle Time					55		70			ns
tAA	Address to Data Valid						55			70	ns
tOHA	Data Hold from Address Change					10		10			ns
tACE		LOW to Data Valid					55			70	ns
	CE
tDOE		LOW to Data Valid					25			35	ns
	OE
t		LOW to Low-Z[10]				5		5			ns
	OE
LZOE
tHZOE		HIGH to High-Z[10, 11]					25			25	ns
	OE
tLZCE		LOW to Low-Z[10]				10		10			ns
	CE
t		HIGH to High-Z[10, 11]					25			25	ns
	CE
HZCE
tPU		LOW to Power-up				0		0			ns
	CE
tPD		HIGH to Power-down					55			70	ns
	CE
tDBE			/		LOW to Data Valid		25			35	ns
	BLE			BHE
tLZBE			/		LOW to Low-Z[10, 11]	5		5			ns
	BLE			BHE
t			/		HIGH to High-Z[12]		25			25	ns
	BLE			BHE
HZBE
Write Cycle[12, 13]
tWC	Write Cycle Time					55		70			ns
tSCE		LOW to Write End				45		60			ns
	CE
tAW	Address Set-up to Write End					45		60			ns
tHA	Address Hold from Write End					0		0			ns
tSA	Address Set-up to Write Start					0		0			ns
tPWE		Pulse Width				40		50			ns
	WE
tBW			/		LOW to Write End	50		60			ns
	BLE			BHE
tSD	Data Set-up to Write End					25		30			ns
tHD	Data Hold from Write End					0		0			ns
t		LOW to High-Z[10, 11]					20			25	ns
	WE
HZWE
tLZWE		HIGH to Low-Z[10]				5		10			ns
	WE

Notes:

9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC typ., and output loading of the specified IOL/IOH and 30-pF load capacitance.

10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

11.tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.

12.The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.

13.The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document #: 001-06510 Rev. *A Page 5 of 12

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