Z9973
Maximum Ratings[3]
Maximum Input Voltage Relative to VSS: | ............ VSS – 0.3V |
Maximum Input Voltage Relative to VDD: | ............. VDD + 0.3V |
Storage Temperature: | |
Operating Temperature: | |
Maximum ESD protection | 2 kV |
Maximum Power Supply: | 5.5V |
Maximum Input Current: | ± 20 mA |
DC Parameters (VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA
This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range:
VSS < (VIN or VOUT) < VDD .
Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
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| Min. | Typ. |
| Max. | Unit |
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VIL | Input LOW Voltage |
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| VSS |
| 0.8 | V | |||
VIH | Input HIGH Voltage |
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| 2.0 |
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| VDD | V | |||
VPP |
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| 300 |
| 1000 | mV | |||||
| PECL_CLK |
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VCMR | Common Mode Range PECL_CLK[9] |
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| VDD – 2.0 |
| VDD – 0.6 | V | ||||||
IIL | Input Low Current[10] |
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| µA | |||
IIH | Input High Current[10] |
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| 120 | µA | |||
VOL | Output Low Voltage[11] |
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| IOL = 20 mA |
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| 0.5 | V | ||||||
VOH | Output High Voltage[11] |
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| IOH = | 2.4 |
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| V | ||||||
IDDQ | Quiescent Supply Current |
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| 10 | 15 | mA | |||
IDDA | PLL Supply Current |
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| VDD only |
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| 15 | 20 | mA | ||||
IDD | Dynamic Supply Current |
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| QA and QB @ 60 MHz, |
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| 225 |
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| QC @ 120 MHz, CL = 30 pF |
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| QA and QB @ 25 MHz, |
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| QC @ 50 MHz, CL = 30 pF |
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CIN | Input Pin Capacitance |
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| 4 |
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AC Parameters (V | = 2.9V to 3.6V, V | DDC | = 3.3V ±10%, T | A | = |
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Parameter |
| Description |
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| Min. | Typ. |
| Max. | Units | ||||
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Tr / Tf |
| TCLK Input Rise / Fall |
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| 3.0 | ns | ||
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Fref |
| Reference Input Frequency |
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| Note 5 |
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| Note 5 | MHz | ||||
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FrefDC |
| Reference Input Duty Cycle |
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| 25 |
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| 75 | % | ||||
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Fvco |
| PLL VCO Lock Range |
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| 200 |
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| 480 | MHz | ||
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Tlock |
| Maximum PLL Lock Time |
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| 10 | ms | ||
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Tr / Tf |
| Output Clocks Rise/Fall Time[6] |
| 0.8V to 2.0V |
| 0.15 |
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| 1.2 | ns | ||||||
Notes:
3.The voltage on any input or I/O pic cannot exceed the power pin during
4.Parameters are guaranteed by design and characterization. Not 100% tested in production.
5.Maximum and minimum input reference is limited by VC0 lock range.
6.Outputs loaded with 30 pF each.
Document #: | Page 6 of 9 |
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