Cypress CY7C132, CY7C136A, CY7C146, CY7C142 manual Right Address Valid First

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CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Switching Waveforms (continued)

Figure 10. Busy Timing Diagram No. 2 (Address Arbitration)

Left Address Valid First:

tRC or tWC

ADDRESSL

ADDRESS MATCH

ADDRESS MISMATCH

tPS

ADDRESSR

R

tBLA

tBHA

BUSY

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSYL

tRC or tWC
ADDRESS MATCH	ADDRESS MISMATCH

tPS

tBLA

tBHA

Figure 11. Busy Timing Diagram No. 3 (Write with BUSY, Slave: CY7C142/CY7C146)

CE

R/W

BUSY

tWB

tPWE

tWH

Document #: 38-06031 Rev. *E

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Contents Functional Description FeaturesLogic Block Diagram Cypress Semiconductor Corporation 198 Champion CourtCom’l/Ind PinoutsSelection Guide Maximum Standby Current Com’l/IndMaximum Ratings Electrical CharacteristicsOperating Range Parameter Description Test Conditions Max Unit Switching CharacteristicsCapacitance Read CycleWrite Cycle Busy/Interrupt Timing7C146-35 7C146-45 7C132-35 7C132-45Write Cycle12 Switching Waveforms Reset Time13Write Cycle No.1 OE Three-States Data I/Os-Either Port 12 Write Cycle No R/W Three-States Data I/Os-Either Port12 CER Valid FirstRight Address Valid First Interrupt Timing Diagrams Left Side Sets IntrTypical DC and AC Characteristics Ordering Information Pin Plastic Leaded Chip Carrier Pin Plastic Quad FlatpackDocument History Sales, Solutions, and Legal InformationSubmission Orig. Description of Change Date