Cypress CY7C142, CY7C132 Write Cycle No R/W Three-States Data I/Os-Either Port12, CER Valid First

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CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Switching Waveforms (continued)

Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[12, 21]

	tWC
ADDRESS
tSCE		tHA
CE
tAW	tPWE
tSA	tPWE
R/W
	tSD	tHD
DATAIN	DATA VALID
t	HZWE	tLZWE
	HZWE

HIGH IMPEDANCE

DOUT

Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)

CEL Valid First:

ADDRESSL,R

CEL

CER

BUSYR

CER Valid First:

ADDRESSL,R

CER

CEL

BUSYL

ADDRESS MATCH
tPS
tBLC	tBHC

ADDRESS MATCH

tPS

tBLC

tBHC

Note

21. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.

Document #: 38-06031 Rev. *E

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Contents Logic Block Diagram FeaturesFunctional Description Cypress Semiconductor Corporation 198 Champion CourtSelection Guide PinoutsCom’l/Ind Maximum Standby Current Com’l/IndElectrical Characteristics Maximum RatingsOperating Range Capacitance Switching CharacteristicsParameter Description Test Conditions Max Unit Read CycleBusy/Interrupt Timing Write Cycle7C132-35 7C132-45 7C146-35 7C146-45Write Cycle12 Reset Time13 Switching WaveformsWrite Cycle No.1 OE Three-States Data I/Os-Either Port 12 CER Valid First Write Cycle No R/W Three-States Data I/Os-Either Port12Right Address Valid First Left Side Sets Intr Interrupt Timing DiagramsTypical DC and AC Characteristics Ordering Information Pin Plastic Quad Flatpack Pin Plastic Leaded Chip CarrierSales, Solutions, and Legal Information Document HistorySubmission Orig. Description of Change Date