Cypress CY7C132, CY7C136A, CY7C146, CY7C142 manual Interrupt Timing Diagrams, Left Side Sets Intr

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CY7C132, CY7C136

CY7C136A, CY7C142, CY7C146

Switching Waveforms (continued)

Interrupt Timing Diagrams [16]

Figure 12. Left Side Sets INTR

ADDRESSL

CEL

R/WL

INTR

	tWC
	WRITE 7FF
tINS	tHA
	tEINS
tSA	tWINS
	tWINS

Figure 13. Right Side Clears INTR

	tRC
ADDRESSR	READ 7FF
tHA	tINR
CER
tEINR
R/WR
OER	tOINR
	tOINR
INTR

Figure 14. Right Side Sets INTL

ADDRESSR

CER

R/WR

INTL

	tWC
	WRITE 7FE
tINS	tHA
	tEINS
tSA	tWINS

Figure 15. Right Side Clears INTL
	tRC
ADDRESSL	READ 7FE
tHA	tINR
CEL
tEINR
R/WL
OEL
	tOINR
INTL
Document #: 38-06031 Rev. *E	Page 11 of 15

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional DescriptionMaximum Standby Current Com’l/Ind PinoutsSelection Guide Com’l/IndOperating Range Electrical CharacteristicsMaximum Ratings Read Cycle Switching CharacteristicsCapacitance Parameter Description Test Conditions Max UnitBusy/Interrupt Timing Write CycleWrite Cycle12 7C132-35 7C132-457C146-35 7C146-45 Reset Time13 Switching WaveformsWrite Cycle No.1 OE Three-States Data I/Os-Either Port 12 CER Valid First Write Cycle No R/W Three-States Data I/Os-Either Port12Right Address Valid First Left Side Sets Intr Interrupt Timing DiagramsTypical DC and AC Characteristics Ordering Information Pin Plastic Quad Flatpack Pin Plastic Leaded Chip CarrierSubmission Orig. Description of Change Date Sales, Solutions, and Legal InformationDocument History