Cypress CY7C1364C manual Write Cycle Timing18,19, Adv

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CY7C1364C

Write Cycle Timing[18,19]

CLK

ADSP

ADSC

ADDRESS

BWE,

BW[A :D]

Data In (D)

Data Out (Q)

tWES tWEH

Note:

19. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW.

Document #: 38-05689 Rev. *E

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Contents Functional Description1 FeaturesCypress Semiconductor Corporation Selection Guide Pin Configuration250 MHz 200 MHz 166 MHz Unit CY7C1364CPin Tqfp Pinout 3 Chip Enables a version Tqfp Pin DefinitionsFunctional Overview Linear Burst Address Table Mode = GND Sleep ModeBurst Sequences First Second Third Fourth AddressAdsp Adsc ADV Address Next Cycle UsedWrite Function Truth Table for Read/Write3BWE BW D BW C BW B BW a Maximum Ratings Electrical Characteristics Over the Operating Range 9Operating Range Thermal Resistance Capacitance11AC Test Loads and Waveforms Switching Characteristics Over the Operating Range12,13 Read Cycle Timing18 Switching WaveformsADV Write Cycle Timing18,19CLZ Read/Write Cycle Timing18,20DON’T Care ZZ Mode Timing22Ordering Information Pin Tqfp 14 x 20 x 1.4 mm Package DiagramDocument History Issue Date Orig. Description of ChangeREV ECN no