Cypress CY7C1364C manual Switching Waveforms, Read Cycle Timing18

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CY7C1364C

Switching Waveforms

CLK

ADSP

ADSC

tCYC

tCH			tCL

tADS tADH

ADDRESS

GW, BWE,

BW[A:D]

Data Out (Q)

Note:

tAS tAH

tWES tWEH

tCES tCEH

tADVS tADVH

Burst continued with new base address

Deselect cycle

ADV suspends burst.

tCHZ

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

Burst wraps around

18. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

Document #: 38-05689 Rev. *E

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Contents Features Functional Description1Cypress Semiconductor Corporation Pin Configuration Selection Guide250 MHz 200 MHz 166 MHz Unit CY7C1364CPin Tqfp Pinout 3 Chip Enables a version Pin Definitions TqfpFunctional Overview Sleep Mode Linear Burst Address Table Mode = GNDBurst Sequences First Second Third Fourth AddressAddress Next Cycle Used Adsp Adsc ADVWrite Truth Table for Read/Write3 FunctionBWE BW D BW C BW B BW a Electrical Characteristics Over the Operating Range 9 Maximum RatingsOperating Range Capacitance11 Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range12,13 Switching Waveforms Read Cycle Timing18Write Cycle Timing18,19 ADVRead/Write Cycle Timing18,20 CLZZZ Mode Timing22 DON’T CareOrdering Information Package Diagram Pin Tqfp 14 x 20 x 1.4 mmIssue Date Orig. Description of Change Document HistoryREV ECN no