Cypress CY7C1345G manual Truth Table, Address Cycle Description, Used

Page 8

CY7C1345G

Truth Table

The truth table for CY7C1345G follows. [1, 2, 3, 4, 5]

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cycle Description

CE1

CE2

 

CE3

ZZ

ADSP

 

ADSC

 

ADV

 

 

WRITE

 

OE

 

CLK

DQ

Used

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

H

X

 

X

L

 

X

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

L

 

X

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

X

 

H

L

 

L

 

X

 

X

 

 

X

 

X

 

L-H

Tri-State

down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

L

L

 

X

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselected Cycle, Power

None

 

X

X

 

X

L

 

H

 

L

 

X

 

 

X

 

X

 

L-H

Tri-State

down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep Mode, Power down

None

 

X

X

 

X

H

 

X

 

X

 

X

 

 

X

 

X

 

X

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

L

 

X

 

X

 

 

X

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Begin Burst

External

 

L

H

 

L

L

 

H

 

L

 

X

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

1.X = “Do Not Care,” H = Logic HIGH, and L = Logic LOW.

2.WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H.

3.The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

4.The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE is driven HIGH prior to the start of the write cycle to enable the outputs to tri-state. OE is a “Do Not Care” for the remainder of the write cycle.

5.OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document Number: 38-05517 Rev. *E

Page 8 of 20

Image 8
Contents Features Functional DescriptionSelection Guide Parameter 133 MHz 100 MHz UnitLogic Block Diagram CLRPin Tqfp Pinout Pin Configurations15CY7C1345G NC/72M NC/36M Ball BGA PinoutNC/576M Pin Definitions Operation. Mode Pin has an internal pull up Functional OverviewStatic No Connects. Not Internally connected to the dieZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitUsed Truth TableAddress Cycle Description Function Truth Table for Read or WritePartial truth table for read or write follows Electrical Characteristics Maximum RatingsOperating Range Range AmbientAC Test Loads and Waveforms CapacitanceThermal Resistance Switching Characteristics Timing Diagrams Shows the read cycle timingWrite Cycle Timing Read/Write Timing ZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm119-Ball BGA 14 x 22 x 2.4 mm Issue Date Orig. Description of Change Document History

CY7C1345G specifications

The Cypress CY7C1345G is a high-performance static random-access memory (SRAM) device designed for various applications requiring fast data access and minimal power consumption. As a member of Cypress's prolific family of SRAMs, the CY7C1345G is particularly noted for its performance in networking and telecommunications.

This device features a 512 Kbit (64 K x 8) memory organization, making it suitable for applications needing moderate amounts of fast-access memory. The CY7C1345G operates at a wide voltage range of 2.7V to 3.6V, accommodating both high-performance and low-power applications. One of its standout attributes is its fast access time, with read cycle times as low as 10 ns, allowing for rapid data retrieval that is essential for modern computing requirements.

Another key feature of the CY7C1345G is its low-power operation mode, making it an excellent choice for battery-operated applications. It has a typical active current of only 35 mA and a standby current of just 3 µA, ensuring prolonged battery life while still maintaining high-performance levels. This low power consumption is complemented by the device's sleep mode functionality, which further reduces power draw during periods of inactivity.

In terms of interface, the CY7C1345G employs a simple asynchronous access protocol, ensuring ease of integration into existing systems without the need for complex timing schemes. The device supports asynchronous read and write operations, with an output enable feature that facilitates efficient data retrieval.

The CY7C1345G is encased in a compact 44-pin TSOP II package, making it suitable for applications where space constraints are critical. Its design adheres to rigorous quality and reliability standards, with the device being fully tested to meet JEDEC specifications.

With its blend of speed, low power consumption, and simple interface, the Cypress CY7C1345G SRAM is ideal for a wide array of applications, including telecommunications systems, networking devices, and embedded systems. As technology drives the demand for faster and more efficient memory solutions, the CY7C1345G stands out as a reliable and versatile choice in the SRAM landscape.