Cypress CY7C1345G manual Pin Definitions

CY7C1345G

Pin Definitions

Name

IO

Description

A0, A1, A

Input

Address Inputs Used to Select One of the 128K Address Locations. Sampled at the rising edge

Synchronous

of the CLK if ADSP or

ADSC

is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed

the two-bit counter.

A,

B

Input

Byte Write Select Inputs, Active LOW. Qualified with

to conduct byte writes to the SRAM.

BW

BW

BWE

BWC, BWD

Synchronous

Sampled on the rising edge of CLK.

Input

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global

GW

Synchronous

write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).

Input

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal is asserted

BWE

Synchronous

LOW to conduct a byte write.

CLK

Input Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

1

Input

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used

in

conjunction with

CE

Synchronous

CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only

when a new external address is loaded.

CE2

Input

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

Synchronous

CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is

loaded.

3

Input

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

CE

Synchronous

CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is

loaded.

Input

Output Enable, asynchronous Input, Active LOW. Controls the direction of the IO pins. When

OE

Asynchronous

LOW, the IO pins act as outputs. When deasserted HIGH, IO pins are tri-stated and act as input data

pins.

OE

is masked during the first clock of a read cycle when emerging from a deselected state.

Input

Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically incre-

ADV

Synchronous

ments the address in a burst cycle.

Input

Address Strobe from Processor, sampled on the rising edge of CLK, Active LOW. When

ADSP

Synchronous

asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are

also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-

nized. ASDP is ignored when CE1 is deasserted HIGH.

Input

Address Strobe from Controller, sampled on the rising edge of CLK, Active LOW. When

ADSC

Synchronous

asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are

also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recog-

nized.

ZZ

Input

ZZ sleep Input, Active HIGH. When asserted HIGH places the device in a non-time critical sleep

Asynchronous

condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin

has an internal pull down.

DQs

IO

Bidirectional Data IO lines. As inputs, they feed into an on-chip data register that is triggered by

DQPA, DQPB

Synchronous

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

DQPC, DQPD

by the addresses presented during the previous clock rise of the read cycle. The direction of the pins

is controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and

DQP[A:D] are placed in a tri-state condition.

VDD

Power Supply

Power supply inputs to the core of the device.

VSS

Ground

Ground for the core of the device.

VDDQ

IO Power

Power supply for the IO circuitry.

Supply

VSSQ

IO Ground

Ground for the IO circuitry.

Document Number: 38-05517 Rev. *E Page 5 of 20