Cypress CY7C1345G manual Features, Functional Description, Selection Guide

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CY7C1345G

4-Mbit (128K x 36) Flow Through Sync SRAM

Features

■128K x 36 common IO

■3.3V core power supply (VDD)

■2.5V or 3.3V IO supply (VDDQ)

■Fast clock-to-output times ❐ 6.5 ns (133 MHz version)

■Provide high performance 2-1-1-1 access rate

■User selectable burst counter supporting Intel Pentium inter- leaved or linear burst sequences

■Separate processor and controller address strobes

■Synchronous self-timed write

■Asynchronous output enable

■Available in Pb-free 100-Pin TQFP package, Pb-free and non-Pb-free 119-Ball BGA package

■ZZ Sleep Mode option

Functional Description

The CY7C1345G is a 128K x 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 6.5 ns (133 MHz version). A two-bit on-chip counter captures the first address in a burst and increments the address automat- ically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive edge triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address pipelining Chip Enable (CE1), depth expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1345G enables either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses are initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) is active. Subsequent burst addresses are internally generated as controlled by the Advance pin (ADV).

The CY7C1345G operates from a +3.3V core power supply while all outputs operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC standard JESD8-5 compatible.

For best practice recommendations, refer to the Cypress appli- cation note AN1064, SRAM System Guidelines.

Selection Guide

Parameter

133 MHz

100 MHz

Unit

Maximum Access Time

6.5

8.0

ns

 

 

 

 

Maximum Operating Current

225

205

mA

 

 

 

 

Maximum Standby Current

40

40

mA

 

 

 

 

Cypress Semiconductor Corporation • 198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Document Number: 38-05517 Rev. *E

 

 

Revised July 15, 2007

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Contents Functional Description FeaturesSelection Guide Parameter 133 MHz 100 MHz UnitCLR Logic Block Diagram15CY7C1345G Pin ConfigurationsPin Tqfp Pinout NC/576M Ball BGA PinoutNC/72M NC/36M Pin Definitions Functional Overview Operation. Mode Pin has an internal pull upStatic No Connects. Not Internally connected to the dieParameter Description Test Conditions Min Max Unit ZZ Mode Electrical CharacteristicsAddress Cycle Description Truth TableUsed Partial truth table for read or write follows Truth Table for Read or WriteFunction Maximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms Switching Characteristics Shows the read cycle timing Timing DiagramsWrite Cycle Timing Read/Write Timing ZZ Mode Timing Ordering Information Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package Diagrams119-Ball BGA 14 x 22 x 2.4 mm Document History Issue Date Orig. Description of Change

CY7C1345G specifications

The Cypress CY7C1345G is a high-performance static random-access memory (SRAM) device designed for various applications requiring fast data access and minimal power consumption. As a member of Cypress's prolific family of SRAMs, the CY7C1345G is particularly noted for its performance in networking and telecommunications.

This device features a 512 Kbit (64 K x 8) memory organization, making it suitable for applications needing moderate amounts of fast-access memory. The CY7C1345G operates at a wide voltage range of 2.7V to 3.6V, accommodating both high-performance and low-power applications. One of its standout attributes is its fast access time, with read cycle times as low as 10 ns, allowing for rapid data retrieval that is essential for modern computing requirements.

Another key feature of the CY7C1345G is its low-power operation mode, making it an excellent choice for battery-operated applications. It has a typical active current of only 35 mA and a standby current of just 3 µA, ensuring prolonged battery life while still maintaining high-performance levels. This low power consumption is complemented by the device's sleep mode functionality, which further reduces power draw during periods of inactivity.

In terms of interface, the CY7C1345G employs a simple asynchronous access protocol, ensuring ease of integration into existing systems without the need for complex timing schemes. The device supports asynchronous read and write operations, with an output enable feature that facilitates efficient data retrieval.

The CY7C1345G is encased in a compact 44-pin TSOP II package, making it suitable for applications where space constraints are critical. Its design adheres to rigorous quality and reliability standards, with the device being fully tested to meet JEDEC specifications.

With its blend of speed, low power consumption, and simple interface, the Cypress CY7C1345G SRAM is ideal for a wide array of applications, including telecommunications systems, networking devices, and embedded systems. As technology drives the demand for faster and more efficient memory solutions, the CY7C1345G stands out as a reliable and versatile choice in the SRAM landscape.
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