Cypress CY7C1345G manual Switching Characteristics

Page 12

CY7C1345G

Switching Characteristics

Over the Operating Range [9, 10]

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

Description

–133

–100

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

POWER

 

V (Typical) to the first Access[11]

1

 

1

 

ms

 

 

DD

 

 

 

 

 

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

7.5

 

10

 

ns

tCH

 

Clock HIGH

2.5

 

4.0

 

ns

tCL

 

Clock LOW

2.5

 

4.0

 

ns

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCDV

 

Data Output Valid After CLK Rise

 

6.5

 

8.0

ns

tDOH

 

Data Output Hold After CLK Rise

2.0

 

2.0

 

ns

tCLZ

 

Clock to Low Z[12, 13, 14]

0

 

0

 

ns

tCHZ

 

Clock to High Z[12, 13, 14]

 

3.5

 

3.5

ns

tOEV

 

 

 

LOW to Output Valid

 

3.5

 

3.5

ns

OE

tOELZ

 

 

 

LOW to Output Low Z[12, 13, 14]

0

 

0

 

ns

OE

tOEHZ

 

 

 

HIGH to Output High Z[12, 13, 14]

 

3.5

 

3.5

ns

OE

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Setup Before CLK Rise

1.5

 

2.0

 

ns

tADS

 

 

 

 

 

 

 

 

 

 

Setup Before CLK Rise

1.5

 

2.0

 

ns

ADSP,

ADSC

tADVS

 

 

 

 

 

Setup Before CLK Rise

1.5

 

2.0

 

ns

ADV

tWES

 

 

 

 

 

 

 

 

 

 

x Setup Before CLK Rise

1.5

 

2.0

 

ns

GW,

BWE,

BW

tDS

 

Data Input Setup Before CLK Rise

1.5

 

2.0

 

ns

tCES

 

Chip Enable Setup

1.5

 

2.0

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold After CLK Rise

0.5

 

0.5

 

ns

tADH

 

 

 

 

 

 

 

 

 

 

Hold After CLK Rise

0.5

 

0.5

 

ns

ADSP,

ADSC

tWEH

 

 

 

 

 

 

 

 

 

 

x Hold After CLK Rise

0.5

 

0.5

 

ns

GW,

BWE,

BW

tADVH

 

 

 

 

Hold After CLK Rise

0.5

 

0.5

 

ns

ADV

tDH

 

Data Input Hold After CLK Rise

0.5

 

0.5

 

ns

tCEH

 

Chip Enable Hold After CLK Rise

0.5

 

0.5

 

ns

Notes

9.Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V.

10.Test conditions shown in (a) of Latch up Current >200 mA unless otherwise noted.

11.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation is initiated.

12.tCHLZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady state voltage.

13.At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions.

14.This parameter is sampled and not 100% tested.

Document Number: 38-05517 Rev. *E

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Contents Features Functional DescriptionSelection Guide Parameter 133 MHz 100 MHz UnitLogic Block Diagram CLRPin Configurations 15CY7C1345GPin Tqfp Pinout Ball BGA Pinout NC/576MNC/72M NC/36M Pin Definitions Operation. Mode Pin has an internal pull up Functional OverviewStatic No Connects. Not Internally connected to the dieZZ Mode Electrical Characteristics Parameter Description Test Conditions Min Max UnitTruth Table Address Cycle DescriptionUsed Truth Table for Read or Write Partial truth table for read or write followsFunction Electrical Characteristics Maximum RatingsOperating Range Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Timing Diagrams Shows the read cycle timingWrite Cycle Timing Read/Write Timing ZZ Mode Timing Ordering Information Package Diagrams Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm119-Ball BGA 14 x 22 x 2.4 mm Issue Date Orig. Description of Change Document History

CY7C1345G specifications

The Cypress CY7C1345G is a high-performance static random-access memory (SRAM) device designed for various applications requiring fast data access and minimal power consumption. As a member of Cypress's prolific family of SRAMs, the CY7C1345G is particularly noted for its performance in networking and telecommunications.

This device features a 512 Kbit (64 K x 8) memory organization, making it suitable for applications needing moderate amounts of fast-access memory. The CY7C1345G operates at a wide voltage range of 2.7V to 3.6V, accommodating both high-performance and low-power applications. One of its standout attributes is its fast access time, with read cycle times as low as 10 ns, allowing for rapid data retrieval that is essential for modern computing requirements.

Another key feature of the CY7C1345G is its low-power operation mode, making it an excellent choice for battery-operated applications. It has a typical active current of only 35 mA and a standby current of just 3 µA, ensuring prolonged battery life while still maintaining high-performance levels. This low power consumption is complemented by the device's sleep mode functionality, which further reduces power draw during periods of inactivity.

In terms of interface, the CY7C1345G employs a simple asynchronous access protocol, ensuring ease of integration into existing systems without the need for complex timing schemes. The device supports asynchronous read and write operations, with an output enable feature that facilitates efficient data retrieval.

The CY7C1345G is encased in a compact 44-pin TSOP II package, making it suitable for applications where space constraints are critical. Its design adheres to rigorous quality and reliability standards, with the device being fully tested to meet JEDEC specifications.

With its blend of speed, low power consumption, and simple interface, the Cypress CY7C1345G SRAM is ideal for a wide array of applications, including telecommunications systems, networking devices, and embedded systems. As technology drives the demand for faster and more efficient memory solutions, the CY7C1345G stands out as a reliable and versatile choice in the SRAM landscape.
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