Jtag Testability | Sun Microsystems SME5224AUPA-400 specification

UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

JTAG TESTABILITY

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), implements the IEEE 1149.1 standard to aid in board level testing. Boundary Scan Description Language (BSDL) ﬁles are available for all the active devices on the module, except the clock buffer.

AC Characteristics - JTAG Timing

400 MHz CPU

10 MHz TCK

Symbol

Parameter

Signals

Conditions

Min

Typ

Max

Units

tW

Test reset pulse width

–

–

–

ns

(TRST)

TRST

[1]

tSU (TDI)

Input setup time to TCK

TDI

–

3

–

ns

tSU (TMS)

Input setup time to TCK

TMS

–

4

–

ns

tH(TDI)

Input hold time to TCK

TDI

–

1.5

–

ns

tH(TMS)

Input hold time to TCK

TMS

–

1.5

–

ns

tPD(TDO)

Output delay from TCK [2]

TDO

IOL = 8 mA

–

6

–

ns

IOH = -4 mA

tOH(TDO)

Output hold time from TCK [2]

TDO

3

–

–

ns

CL = 35 pF

VLOAD = 1.5V

1.TRST is an asynchronous reset.

2.TDO is referenced from falling edge of TCK.

22

Sun Microsystems, Inc

July 1999

Image 22

Sun Microsystems SME5224AUPA-400 manual Jtag Testability, AC Characteristics Jtag Timing

Contents

Ease of System Design Module Features Module BeneﬁtsModule Description Performance CPU Description CPU Features CPU BeneﬁtsUltraSPARC-II CPU External Cache Description Data Buffer DescriptionUltraSPARC-II Data Buffer UDB-II Block Diagram Module Component Overview System Interface UPA Connector PinsUPA Interconnect Module ID Module PowerJtag Interface System Interface Signal DescriptionSignal Type Name and Function Clock Interface JTAG/Debug Interface Miscellaneous SignalsInitialization Interface System Clock Distribution Module ClocksSystem Clocks Tested CPU to UPA Clock Signal Distribution Symbol Parameter Min Typ Max Units Electrical CharacteristicsSymbol Parameter Rating Units Absolute Maximum Ratings Module Power Consumption DC CharacteristicsSymbol Parameter Conditions Min Typ Max Units UPA Data Bus Spice Model Module System Loading Example for UPADATA, Upaecc Cpuclk Module Clock Setup and Hold Time SpeciﬁcationsUpaclk Module Clocks Clock Buffers Timing Measurement Waveforms Propagation Delay, Output Hold Time SpeciﬁcationsMin Max Unit Mechanical Specifications CPU Module Components CPU Module Side View Thermal Specifications Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Term Deﬁnition Speciﬁcation Comments Air Velocity Speciﬁcations Temperature Estimating and Measuring MethodsAirﬂow Cooling Measurement Method Air Velocity Case Temperature Measuring Method Heatsink Temperature Measuring Method MHz CPU MHz TCK Symbol Parameter Signals Conditions AC Characteristics Jtag TimingJtag Testability Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View Pin UPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1 Handling CPU Modules Storage and Shipping SpecificationValue Parameter Conditions Min Typ Part Number CPU Speeds Description Ordering InformationDocument Revision History Date Document No Change Sun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc