System Interface | Sun Microsystems SME5224AUPA-400 manual

UltraSPARC™-II CPU Module	Advanced Version
400 MHz CPU, 4.0 MB E-Cache	SME5224AUPA-400

SYSTEM INTERFACE

Figure 2 shows the major components of a UPA based uniprocessor system. The system controller [1] for the UPA bus arbitrates between the UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, and the I/O bridge chip. The ﬁgure also illustrates a slave-only UPA graphics port for Sun graphics boards.

The module UPA system interface signals run at one-quarter of the rate of the internal CPU frequency.

	UltraSPARC-II
	Module
	SME5224AUPA-400
	UPA Address Bus 0		System	UPA Address Bus 1	UPA
	UPA Address Bus 0		System	UPA Address Bus 1	Graphic
	144		Controller		Graphic
			Controller		Device
					Device
	I/O Bridge	UPA Data Bus		UPA Data Bus
	Chip		72
			72
		UPA Data Bus
			72

				Memory Data Bus
	Cross Bar			Memory Data Bus
	Switch

Memory

SIMMs

Expansion Bus

Figure 2. Uniprocessor System Conﬁguration

UPA Connector Pins

The UPA edge connector provides impedance control. The pin assignments are shown with the physical mod- ule connector and are represented on page 24 and page 25.

UPA Interconnect

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), supports full master and slave functionality with a 128-bit data bus and a 16-bit error correction code (ECC).

All signals that interface with the system are compatible with LVTTL levels. The clock inputs at the module connector, CPU_CLK, UPA_CLK0, and UPA_CLK1, are differential low-voltage PECL compatible.

1.Only two megabytes of external cache are recognized and supported when using the Dual Processor System Controller (DSC, Marketing Part No.STP2202ABGA).

July 1999

Sun Microsystems, Inc

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Sun Microsystems SME5224AUPA-400 manual System Interface, UPA Connector Pins, UPA Interconnect

Contents

Module Description Module Features Module BeneﬁtsEase of System Design Performance UltraSPARC-II CPU CPU Features CPU BeneﬁtsCPU Description UltraSPARC-II Data Buffer UDB-II Data Buffer DescriptionExternal Cache Description Module Component Overview Block Diagram UPA Interconnect UPA Connector PinsSystem Interface Jtag Interface Module PowerModule ID Signal Type Name and Function Signal DescriptionSystem Interface Clock Interface Initialization Interface Miscellaneous SignalsJTAG/Debug Interface System Clocks Module ClocksSystem Clock Distribution Tested CPU to UPA Clock Signal Distribution Symbol Parameter Rating Units Electrical CharacteristicsSymbol Parameter Min Typ Max Units Absolute Maximum Ratings Symbol Parameter Conditions Min Typ Max Units DC CharacteristicsModule Power Consumption Module System Loading Example for UPADATA, Upaecc UPA Data Bus Spice Model Upaclk Module Clocks Setup and Hold Time SpeciﬁcationsCpuclk Module Clock Clock Buffers Min Max Unit Propagation Delay, Output Hold Time SpeciﬁcationsTiming Measurement Waveforms CPU Module Components Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Specifications Term Deﬁnition Speciﬁcation Comments Thermal Deﬁnitions and Speciﬁcations Airﬂow Cooling Measurement Method Temperature Estimating and Measuring MethodsAir Velocity Speciﬁcations Air Velocity Heatsink Temperature Measuring Method Case Temperature Measuring Method Jtag Testability AC Characteristics Jtag TimingMHz CPU MHz TCK Symbol Parameter Signals Conditions Jtag Ieee 1149.1 Timing Pin UPA Connector PIN Assignments TOP View Vddcore GND Vddcore GND Vddcore UPAPORTID1 UPA Connector PIN Assignments Bottom View Value Parameter Conditions Min Typ Storage and Shipping SpecificationHandling CPU Modules Document Revision History Ordering InformationPart Number CPU Speeds Description Date Document No Change Sun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc