Sun Microsystems SME5224AUPA-400 S YSTEM I

5

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

SYSTEM INTERFACE

Figure2 shows the major components of a UPA based uniprocessor system. The system controller [1] for the

UPAbus arbitrates between the UltraSPARC™–II,400 MHz CPU, 4.0 Mbyte module, and the I/O bridge chip.

The ﬁgure also illustrates a slave-only UPA graphics port for Sun graphics boards.

The module UPA system interface signals run at one-quarter of the rate of the internal CPU frequency.

UPA Connector Pins

TheUPA edge connector provides impedance control. The pin assignments are shown with the physical mod-

ule connector and are represented on page 24 and page 25.

UPA Interconnect

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), supports full master and

slave functionality with a 128-bit data bus and a 16-bit error correction code (ECC).

All signals that interface with the system are compatible with LVTTL levels. The clock inputs at the module

connector, CPU_CLK, UPA_CLK0, and UPA_CLK1, are differential low-voltage PECL compatible.

1. Only two megabytes of external cache are recognized and supported when using the

Dual Processor System Controller (DSC, Marketing Part No.STP2202ABGA).

Figure 2. Uniprocessor System Conﬁguration

I/O Bridge

Chip

UltraSPARC-II

Module

SME5224AUPA-400

Memory

SIMMs

Memory Data Bus

Cross Bar

Switch

UPA Address Bus 0

UPA Data Bus

144

72

UPA Data Bus

72

Expansion Bus

UPA

Graphic

Device

System

Controller UPA Address Bus 1

UPA Data Bus

Contents

Main DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page S IGNAL D System Interface 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H Page DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page 7 S IGNAL D 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. System Interface Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions 12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times 24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H