Sun Microsystems SME5224AUPA-400 UPA Data Bus SPICE Model

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

UPA Data Bus SPICE Model

A typical circuit for the UPA data bus and ECC signals is illustrated inFigure 4:.

Figure 4. Module System Loading: Example for UPA_DATA, UPA_ECC

3.1 nH

1.0 pF

Edge Connector

UDB-II Driver

Trace 1

0.5 nH 2 nH

50Ω

via 0.6 pF

7 pF

Trace 2

XB1 BGA Package Loading

3.1 nH

Edge Connector

Trace 3

0.5 nH 2 nH

50Ω

via 0.6 pF

7 pF

UDB-II of Second Module

Package Loading

Trace 4

Measure point for XB1

Measure point for CPU

WorstCase: Z0=60Ω,T

P=180 ps/inch, Trace 1 Length = 4.4”, Trace2 Length = 0.6”, Trace 3 Length

= 1.2”, Trace 4 Length = 4.4”

BestCase: Z0=50Ω,T

P=160 ps/inch, Trace 1 Length = 2.2”, Trace 2 Length = 0.2”, Trace3 Length

= 0.2”, Trace 4 Length = 2.2”

1.0 pF

1.0 pF1.0 pF

Contents

Main DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page S IGNAL D System Interface 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H Page DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page 7 S IGNAL D 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. System Interface Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions 12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times 24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H