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Module ID
Module IDs are used to configure the UPA address of a module. The UPA_PORT_ID[4:3] are hardwired on the module to “0”. UPA_PORT_ID[1:0] are brought out to the connector pins. Each module is hardwired in the system to a fixed and unique UPA address. This feature supports systems with four or fewer processors. For systems that need to support eight modules, UPA_SPEED[1] is connected to SYSID[2] in
Systems which support more than eight modules must map the limited set of UPA_PORT_IDs from this mod- ule to the range of required UPA_PORT_IDs, by
System firmware (Open Boot Prom) uses UPA_CONFIG_REG[42:39] for generating correct clocks to the CPU module and the UPA system ASICs. These bits are hardwired on the module and are known at MCAP[3:0] at the
Module Power
Two types of power are required for this module: VDD at 3.3V, and VDD_CORE at 2.6V. The VDD_CORE supplies the
interface I/O, and the SRAM I/O. A resistor located on the module sends the program value to the power supply so it generates VDD_CORE at 2.6V to the regulator.
JTAG Interface
The JTAG TCK signal is distributed to
6 | Sun Microsystems, Inc | July 1999 |