Block Diagram | Sun Microsystems SME5224AUPA-400 specification

UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

MODULE COMPONENT OVERVIEW

The UltraSPARC™–II, 400 MHz CPU, 4.0 Mbyte module, (SME5224AUPA-400), (see Figure 1), consists of the following components:

•UltraSPARC™-II CPU at 400 MHz

•UltraSPARC-II Data Buffer (UDB-II)

•4.0 Megabyte E-cache, made up of eight (256K X 18) data SRAMs and one 128K X 36 Tag SRAM

•Clock Buffer: MC100LVE210

•DC-DC regulator (2.6V to 1.9V)

•Module Airﬂow Shroud

Block Diagram

The module block diagram for the UltraSPARC™–II, 400 MHz CPU, 4 Mbyte E-cache module is illustrated in Figure 1.

Tag SRAM ADDR [17:0] + Control

Tag SRAM DATA [24:0]

UltraSPARC-II

CPU

UPA ADDR [35:0] + Control

Tag SRAM 128K x 36

	1.9V
	DC-DC	Clock Buffer
	Regulator	Clock Buffer
	Regulator

	SRAM ADDR [19:0] + Control
SRAM	SRAM
256K x 18	256K x 18

DATA [143:72]	DATA [71:0]
UDB-II	UDB-II
	UDB-II
	Control

2.6V

Clocks

UPA_DATA [143:0]

UPA Connector

Figure 1. Module Block Diagram

4

Sun Microsystems, Inc

July 1999

Image 32

Sun Microsystems SME5224AUPA-400 manual Block Diagram

Contents

Module Features Module Beneﬁts Module DescriptionEase of System Design Performance UltraSPARC-II CPU CPU Features CPU BeneﬁtsCPU Description UltraSPARC-II Data Buffer UDB-II Data Buffer DescriptionExternal Cache Description Block Diagram Module Component Overview UPA Interconnect UPA Connector PinsSystem Interface Jtag Interface Module PowerModule ID Signal Description Signal Type Name and FunctionSystem Interface Clock Interface Initialization Interface Miscellaneous SignalsJTAG/Debug Interface Module Clocks System ClocksSystem Clock Distribution Tested CPU to UPA Clock Signal Distribution Electrical Characteristics Symbol Parameter Rating UnitsSymbol Parameter Min Typ Max Units Absolute Maximum Ratings Symbol Parameter Conditions Min Typ Max Units DC CharacteristicsModule Power Consumption UPA Data Bus Spice Model Module System Loading Example for UPADATA, Upaecc Setup and Hold Time Speciﬁcations Upaclk Module ClocksCpuclk Module Clock Clock Buffers Min Max Unit Propagation Delay, Output Hold Time SpeciﬁcationsTiming Measurement Waveforms Mechanical Specifications CPU Module Components CPU Module Side View Thermal Specifications Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Term Deﬁnition Speciﬁcation Comments Temperature Estimating and Measuring Methods Airﬂow Cooling Measurement MethodAir Velocity Speciﬁcations Air Velocity Case Temperature Measuring Method Heatsink Temperature Measuring Method Jtag Testability AC Characteristics Jtag TimingMHz CPU MHz TCK Symbol Parameter Signals Conditions Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View Pin UPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1 Value Parameter Conditions Min Typ Storage and Shipping SpecificationHandling CPU Modules Ordering Information Document Revision HistoryPart Number CPU Speeds Description Date Document No Change Sun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc