Sun Microsystems SME5224AUPA-400 E LECTRICAL C

11

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings [1]

1. Operation of the device at values in excess of those listed above will result in degradation or destruction of the device. All voltages

aredeﬁned with respect to ground. Functional operation of the device at these or any other conditions beyondthose indicated under

“recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may

affect device reliability.

Symbol Parameter Rating Units

VDD Supply voltage range for I/O 0 to 3.8 V

VDD_CORE [2]

2. The VDD_CORE supplies voltage to the onboard DC-DC regulator. The onboard DC-DC regulator then powers the CPU core and the

SRAMI/O bus interface. The VDD_CORE must be lower than VDD,except when the CPU is being re-cycled, at which time the VDD can

be lower than VDD_CORE for 30 ms or less, provided that the current is limited to twice thew maximum CPU rating.

Supply voltage range for CPU core 0 to 3.0 V

VIInput voltage range [3]

3. Unless otherwise noted, all voltages are with respect to the VSSground.

-0.5 to VDD + 0.5 V

VOOutput voltage range -0.5 to VDD + 0.5 V

IIK Input clamp current ±20 mA

IOK Output clamp current ±50 mA

IOL Current into any output in the low state 50 mA

TSTG Storage temperature (non-operating) -40 to 90 °C

Recommended Operating Conditions

Symbol Parameter Min Ty p Max Units

VDD Supply voltage for I/O 3.14 3.30 3.46 V

VDD_CORE Supply voltage for the CPU core [1]

1. A current of 2.6V supplies power to the DC-DC regulator which in turn supplies 1.9V to the CPU core.

2.47 2.60 2.73 V

VSS Ground – 0 – V

VIH High-level input voltage 2.0 – VDD + 0.2 V

VIL Low-level input voltage -0.3 – 0.8 V

IOH High-level output current – – -4 mA

IOL Low-level output current – – 8 mA

TJOperating junction temperature – – 85 °C

TAOperating ambient temperature – – – [2]

2. Maximum ambient temperature is limited by airﬂow such that the maximum junction temperature does not exceed TJ. See the section

"Thermal Speciﬁcations," on page 18.

°C

Contents

Main DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page S IGNAL D System Interface 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H Page DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page 7 S IGNAL D 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. System Interface Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions 12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times 24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H