Sun Microsystems SME5224AUPA-400 D ATA B UFFER D, E XTERNAL C ACHE D

3

400 MHz CPU, 4.0 MB E-Cache

UltraSPARC™-II CPU Module SME5224AUPA-400

Advanced Version

July 1999 Sun Microsystems, Inc

DATA BUFFER DESCRIPTION

UltraSPARC-II Data Buffer (UDB-II)

TheUltraSPARC™-II module has two UltraSPARC-II data buffers (UDB-II) - each a 256 pin BGA device - for

a UPA Interconnect system bus width of 128 Data + 16 ECC.

Thereis a bidirectional ﬂow of information between the external cache of the CPU and the 144-bit UPA inter-

connect.The information ﬂow is linked through the UDB-II, it includes: cache ﬁll requests, writeback data for

dirtydisplaced cache lines, copyback data for cache entries requested by the system, non-cacheable loads and

stores, and interrupt vectors going to and from the CPU.

EachUDB-II has a 64-bit interface plus eight parity bits on the CPU side, and a 64-bit interface plus eight error

correction code (ECC) bits on the system side.

The CPU side of the UDB-II is clocked with the same clock delivered to UltraSPARC-II (1/2 of the CPU pipe-

line frequency).

EXTERNAL CACHE DESCRIPTION

The external cache is connected to the E-cache data bus. Nine SRAM chips are used to implement the four

megabyte cache. One SRAM is used as the tag SRAM and eight are used as data SRAMs. The tag SRAM is

128Kx 36, while the data SRAMs are 256K x 18. All nine SRAMs operate in synchronous register-latch mode.

The SRAM interface to the CPU runs at one-half of the frequency of the CPU pipeline. The SRAM signals

operate at 1.9V HSTL. The SRAM clock is a differential low-voltage HSTL input. [1]

1. PECL (Positive Emitter Coupled Logic) clocks are converted on the module to the HSTL clocks, for the E-cache

interface.

Contents

Main DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page S IGNAL D System Interface 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H Page DATASHEET SME5224AUPA-400 UltraSPARC-II CPU Module 400 MHz CPU, 4.0 MB E-Cache MODULE DESCRIPTION Module Features Module Benets CPU D UltraSPARC-II CPU CPU Features CPU Benets D ATA B UFFER D E XTERNAL C ACHE D M ODULE COMPONENT O Block Diagram S YSTEM I Page 7 S IGNAL D 1. For the modular connector pin assignments (UPA pin-out assignments) see page 24 and page 25. System Interface Clock Interface JTAG/Debug Interface Initialization Interface Miscellaneous Signals UPAAND CPU CLOCKS Module Clocks System Clocks System Clock Distribution Page E LECTRICAL C Absolute Maximum Ratings Recommended Operating Conditions 12 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache Module Power Consumption DC Characteristics UPA Data Bus SPICE Model U P AA CT UPA_CLK Module Clocks CPU_CLK Module Clock Clock Buffers Timing References Timing Measurement Waveforms Figure 5. Timing Measurement Waveforms Propagation Delay, Output Hold Time Specications MECHANICAL SPECIFICATIONS The module components and dimensions are specied inFigure 6,Figure 7,Figure 8 and Figure9. Figure 7. CPU Module (Component Dimensions) Figure 6. CPU Module Components Page T HERMAL S Two Step Approach to Thermal Design Thermal Denitions and Specications Temperature Estimating and Measuring Methods Page JTAGT AC Characteristics - JTAG Timing JTAG(IEEE 1149.1) T Figure 10. Voltage Waveforms - Setup and Hold Times Figure 11. Voltage Waveforms - Propagation Delay Times 24 SME5224AUPA-400 400 MHz CPU, 4.0 MB E-Cache UPACONNECTOR PIN ASSIGNMENTS (TOP VIEW) UPACONNECTOR PIN ASSIGNMENTS (BOTTO M VIEW) H ANDLING CPU M S TORAGEAND S HIPPING S ORDERING INFORMATION[1] D OCUMENT R EVISION H