JTAG/Debug Interface | Sun Microsystems SME5224AUPA-400 instruction

UltraSPARC™-II CPU Module

SME5224AUPA-400400 MHz CPU, 4.0 MB E-Cache

JTAG/Debug Interface

Signal	Type	Name and Function
TDO	O	IEEE 1149 test data output. A three-state signal driven only when the TAP controller is
		in the shift-DR state.

TDI	I	IEEE 1149 test data input. This pin is internally pulled to logic one when not driven.

TCK	I	IEEE 1149 test clock input. This pin if not hooked to a clock source must always be
		driven to a logic 1 or a logic 0.

TMS	I	IEEE 1149 test mode select input. This pin is internally pulled to logic one when not
		driven. Active high.

TRST_L	I	IEEE 1149 test reset input (active low). This pin is internally pulled to logic one when not
		driven. Active low.

Initialization Interface

Signal	Type	Name and Function
UPA_RESET_L	I	Driven by the system controller for the POR (power-on) resets and the fatal system
		reset. Asserted asynchronously. Deasserted synchronous to UPA_CLK. Active low.

UPA_XIR_L	I	Driven to signal externally initiated reset (XIR). Actually acts like a non-maskable
		interrupt. Synchronous to UPA_CLK. Active low, asserted for one clock cycle.

Miscellaneous Signals

Signal	Type	Name and Function
TEMP_SENSE_NEG	O	Connected to a thermistor [1] adjacent to the CPU package.
TEMP_SENSE_POS

POWER_SET_POS	O	POWER_SET_NEG is tied to GND on the module. POWER_SET_POS is connected
POWER_SET_NEG		to GND via a 1690-ohm resistor. Sets voltage of programmable supply.

POWER_OV	O	Connected to GND via a 1180-ohm resistor. Sets overvoltage level for programmable
		supply.

1.The thermistor used on the module (SME5224AUPA-400) is manufactured by KOA. Operating at 47K the thermistor has KOA part number NT32BT473J.

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Sun Microsystems, Inc

July 1999

Image 36

Sun Microsystems SME5224AUPA-400 manual JTAG/Debug Interface

Contents

Module Features Module Beneﬁts Module DescriptionEase of System Design Performance CPU Features CPU Beneﬁts CPU DescriptionUltraSPARC-II CPU Data Buffer Description External Cache DescriptionUltraSPARC-II Data Buffer UDB-II Block Diagram Module Component Overview UPA Connector Pins System InterfaceUPA Interconnect Module Power Module IDJtag Interface Signal Description Signal Type Name and FunctionSystem Interface Clock Interface Miscellaneous Signals JTAG/Debug InterfaceInitialization Interface Module Clocks System ClocksSystem Clock Distribution Tested CPU to UPA Clock Signal Distribution Electrical Characteristics Symbol Parameter Rating UnitsSymbol Parameter Min Typ Max Units Absolute Maximum Ratings DC Characteristics Module Power ConsumptionSymbol Parameter Conditions Min Typ Max Units UPA Data Bus Spice Model Module System Loading Example for UPADATA, Upaecc Setup and Hold Time Speciﬁcations Upaclk Module ClocksCpuclk Module Clock Clock Buffers Propagation Delay, Output Hold Time Speciﬁcations Timing Measurement WaveformsMin Max Unit Mechanical Specifications CPU Module Components CPU Module Side View Thermal Specifications Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Term Deﬁnition Speciﬁcation Comments Temperature Estimating and Measuring Methods Airﬂow Cooling Measurement MethodAir Velocity Speciﬁcations Air Velocity Case Temperature Measuring Method Heatsink Temperature Measuring Method AC Characteristics Jtag Timing MHz CPU MHz TCK Symbol Parameter Signals ConditionsJtag Testability Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View Pin UPA Connector PIN Assignments Bottom View Vddcore GND Vddcore GND Vddcore UPAPORTID1 Storage and Shipping Specification Handling CPU ModulesValue Parameter Conditions Min Typ Ordering Information Document Revision HistoryPart Number CPU Speeds Description Date Document No Change Sun Microsystems, Inc UltraSPARC -II CPU Module UltraSPARC-II CPU Data Buffer Description Block Diagram System Interface Module ID System Interface JTAG/Debug Interface UPA and CPU Clocks Clock Signal Distribution Absolute Maximum Ratings DC Characteristics UPA Data Bus Spice Model Upaclk Module Clocks Propagation Delay, Output Hold Time Speciﬁcations Mechanical Specifications CPU Module Side View Two Step Approach to Thermal Design Thermal Deﬁnitions and Speciﬁcations Temperature Estimating and Measuring Methods Case Temperature Measuring Method AC Characteristics Jtag Timing Jtag Ieee 1149.1 Timing UPA Connector PIN Assignments TOP View UPA Connector PIN Assignments Bottom View Storage and Shipping Specification Ordering Information Sun Microsystems, Inc