Cypress CY7C68023, CY7C68024 manual Ddo

Page 3

CY7C68023/CY7C68024

3.2Pin Descriptions (continued)

Pin

Name

Type

Default State at Start-up

Description

16

Reserved

N/A

N/A

Must be tied HIGH (no pull-up resistor required)

 

 

 

 

 

17

VCC

PWR

PWR

3.3V supply

 

 

 

 

 

18

DDO

I/O

Z

Data 0

 

 

 

 

 

19

DD1

I/O

Z

Data 1

 

 

 

 

 

20

DD2

I/O

Z

Data 2

 

 

 

 

 

21

DD3

I/O

Z

Data 3

 

 

 

 

 

22

DD4

I/O

Z

Data 4

 

 

 

 

 

23

DD5

I/O

Z

Data 5

 

 

 

 

 

24

DD6

I/O

Z

Data 6

 

 

 

 

 

25

DD7

I/O

Z

Data 7

 

 

 

 

 

26

GND

GND

GND

Ground

 

 

 

 

 

27

VCC

PWR

PWR

3.3V supply

 

 

 

 

 

28

GND

GND

GND

Ground

 

 

 

 

 

29

WE#

O

H

Write enable

 

 

 

 

 

30

RE0#

O

H

Read Enable 0

 

 

 

 

 

31

RE1#

O

H

Read Enable 1

 

 

 

 

 

32

VCC

PWR

PWR

3.3V supply

 

 

 

 

 

33

CLE

O

Z

Command latch enable

 

 

 

 

 

34

ALE

O

Z

Address latch enable

 

 

 

 

 

35

LED1#

O

Z

Data activity LED sink

 

 

 

 

 

36

LED2#

O

Z

Chip active LED sink

 

 

 

 

 

37

WP_NF#

O

Z

Write-protect NAND Flash

 

 

 

 

 

38

WP_SW#

I

Z

Write-protect switch input

 

 

 

 

 

39

N/C

N/A

N/A

No connect

 

 

 

 

 

40

N/C

N/A

N/A

No connect

 

 

 

 

 

41

GND

GND

GND

Ground

 

 

 

 

 

42

RESET#

I

Z

NX2LP chip reset

 

 

 

 

 

43

VCC

PWR

PWR

3.3V supply

 

 

 

 

 

44

Reserved

N/A

N/A

Must be tied HIGH

 

 

 

 

 

45

CE0#

O

Z

Chip enable 0

 

 

 

 

 

46

CE1#

O

Z

Chip enable 1

 

 

 

 

 

47

CE2#

O

Z

Chip enable 2

 

 

 

 

 

48

CE3#

O

Z

Chip enable 3

 

 

 

 

 

49

CE4#

O

Z

Chip enable 4

 

 

 

 

 

50

CE5#

O

Z

Chip enable 5

 

 

 

 

 

51

CE6#

O

Z

Chip enable 6

 

 

 

 

 

52

CE7#

O

Z

Chip enable 7

 

 

 

 

 

53

GND

GND

GND

Ground

 

 

 

 

 

54

N/C

N/A

N/A

No connect

 

 

 

 

 

55

VCC

PWR

PWR

3.3V supply

 

 

 

 

 

56

GND

GND

GND

Ground

 

 

 

 

 

Document #: 38-08055 Rev. *B

Page 3 of 9

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Contents Introduction FeaturesPin Descriptions Pin DiagramPin Name Type Default State at Start-up Description Pin AssignmentsDDO Additional Pin Descriptions XTALIN, Xtalout DiagramApplications Functional OverviewEnumeration Operating Conditions2 Design Notes For The Quad Flat No Lead QFN PackagePCB Layout Recommendations Absolute Maximum RatingsUSB Transceiver DC CharacteristicsAC Electrical Characteristics Ordering InformationPackage Diagram Disclaimers, Trademarks, and CopyrightsLead QFN 8 x 8 MM LF56A Document History Issue Orig. Description of Change Date