Cypress CY62157ESL Switching Characteristics, Parameter Read Cycle Description 45 ns Min Max Unit

CY62157ESL MoBL®

Switching Characteristics

Over the Operating Range [9]

Parameter

Read Cycle

Description

45 ns

Min Max

Unit

tRC	Read Cycle Time		45		ns
tAA	Address to Data Valid			45	ns
tOHA	Data Hold from Address Change		10		ns
tACE		LOW to Data Valid		45	ns
	CE
tDOE		LOW to Data Valid		22	ns
	OE
tLZOE		LOW to LOW-Z[10]	5		ns
	OE
tHZOE		HIGH to High-Z[10, 11]		18	ns
	OE
tLZCE		LOW to Low-Z[10]	10		ns
	CE
tHZCE		HIGH to High-Z[10, 11]		18	ns
	CE
tPU		LOW to Power Up	0		ns
	CE
tPD		HIGH to Power Down		45	ns
	CE
tDBE				45	ns
	BLE/BHE LOW to Data Valid
tLZBE			5		ns
	BLE/BHE LOW to Low-Z[10,12]
tHZBE				18	ns
	BLE/BHE HIGH to HIGH-Z[10,11]
Write Cycle[13]
tWC	Write Cycle Time		45		ns
tSCE		LOW to Write End	35		ns
	CE
tAW	Address Setup to Write End		35		ns
tHA	Address Hold from Write End		0		ns
tSA	Address Setup to Write Start		0		ns
tPWE		Pulse Width	35		ns
	WE
tBW			35		ns
	BLE/BHE LOW to Write End
tSD	Data Setup to Write End		25		ns
tHD	Data Hold from Write End		0		ns
tHZWE		LOW to High-Z[10, 11]		18	ns
	WE
tLZWE		HIGH to Low-Z[10]	10		ns
	WE

Notes

9.Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 4.

10.At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.

11.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.

12.If both byte enables are toggled together, this value is 10 ns.

13.The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 001-43141 Rev. ** Page 6 of 12

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