Cypress CY62157ESL manual Features, Functional Description, Logic Block Diagram

Features

■Very high speed: 45 ns

■Wide voltage range: 2.2V–3.6V and 4.5V–5.5V

■Ultra low standby power

❐Typical Standby current: 2 μA

❐Maximum Standby current: 8 μA

■Ultra low active power

❐Typical active current: 1.8 mA at f = 1 MHz

■Easy memory expansion with CE and OE features

■Automatic power down when deselected

■CMOS for optimum speed and power

■Available in Pb-free 44-pin TSOP II package

CY62157ESL MoBL®

8-Mbit (512K x 16) Static RAM

into standby mode when deselected (CE HIGH or both BHE and BLE are HIGH). The input or output pins (IO0 through IO15) are placed in a high impedance state when:

■Deselected (CE HIGH)

■Outputs are disabled (OE HIGH)

■Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH)

■Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A18).

Functional Description

The CY62157ESL is a high performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Place the device

To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 10 for a complete description of read and write modes.

For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Logic Block Diagram

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

ROW DECODER

DATA IN DRIVERS

512K x 16 RAM Array

SENSE AMPS

IO0–IO7

IO8–IO15

Power Down

Circuit

		COLUMN DECODER
CE
									BHE
									WE
BHE									CE
	11	12	13	14	15	16	17	18
BLE	A A A A				A A A			A	OE
									BLE

Cypress Semiconductor Corporation • 198 Champion Court	•	San Jose, CA 95134-1709	•	408-943-2600
Document #: 001-43141 Rev. **		Revised January 04, 2008

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