Cypress CY14E102N, CY14E102L manual Switching Waveforms

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ADVANCE

CY14E102L, CY14E102N

 

 

 

 

 

 

 

 

 

 

Switching Waveforms

Figure 5. SRAM Read Cycle #1: Address Controlled[12, 13, 23]

ADDRESS

tRC

tAA

tOHA

DQ (DATA OUT)

DATA VALID

Figure 6. SRAM Read Cycle #2: CE and OE Controlled[12, 23, 25]

ADDRESS

CE

OE

BHE , BLE

DQ (DATA OUT)

ICC

tRC

tACE

tLZCE

tDOE

tLZOE

tDBE

tLZBE

tPU ACTIVE

STANDBY

tPD

tHZCE

tHZOE

tHZCE tHZBE

DATA VALID

Notes

23.HSB must remain HIGH during READ and WRITE cycles.

24.CE or WE must be >VIH during address transitions.

25.BHE and BLE are applicable for x16 configuration only.

Document Number: 001-45755 Rev. *A

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional DescriptionNot to Scale PinoutsX16 Pin Definitions AutoStore Operation Device OperationSram Read Sram WriteSoftware Store Hardware Recall Power UpMode Selection A15 A0 Mode PowerNoise Considerations Mode Selection A15 A0 PowerPreventing AutoStore Data ProtectionRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions CapacitanceThermal Resistance AC Test LoadsSram Write Cycle AC Switching CharacteristicsMin Max Parameters Sram Read Cycle Hardware Store Cycle AutoStore and Power Up RecallSoftware Controlled Store and Recall Cycle Switching Waveforms Switching Waveforms AutoStore or Power Up RECALL26 Α α Ordering Information CY14E102L-BA25XIT CY14E102L-ZS25XCTCY14E102L-ZS25XIT CY14E102N-BA25XCTNvsram Part Numbering NomenclatureCY 14 E 102 L ZS P 15 X C T ZS TsopPin Tsop Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Orig. Submission Description of Change Sales, Solutions, and Legal InformationDocument History
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