Cypress CY14E102L, CY14E102N manual Switching Waveforms

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Switching Waveforms (continued)
	Figure 7. SRAM Write Cycle #1: WE Controlled[13, 21, 22, 23]
		tWC
ADDRESS
		tSCE	tHA
		tSCE
CE
		tAW
	tSA	tPWE
WE		tPWE
WE
BHE , BLE		tBW
BHE , BLE
		tSD	tHD
DATA IN		DATA VALID
		tHZWE	tLZWE
		HIGH IMPEDANCE	tLZWE
DATA OUT	PREVIOUS DATA	HIGH IMPEDANCE
DATA OUT	PREVIOUS DATA

Figure 8. SRAM Write Cycle #2: CE Controlled[13, 21, 22, 23]

ADDRESS

tSA

BHE , BLE

DATA IN

tWC

tSCE

tAW

tPWE

tBW

tSD

DATA VALID

tHA

tHD

DATA OUT

HIGH IMPEDANCE

Document Number: 001-45755 Rev. *A

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Contents Features Logic Block DiagramFunctional Description Cypress Semiconductor Corporation 198 Champion CourtPinouts X16Not to Scale Pin Definitions Device Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Mode SelectionA15 A0 Mode Power Software StoreMode Selection A15 A0 Power Preventing AutoStoreData Protection Noise ConsiderationsDC Electrical Characteristics Maximum RatingsOperating Range RangeCapacitance Thermal ResistanceAC Test Loads AC Test ConditionsAC Switching Characteristics Min Max Parameters Sram Read CycleSram Write Cycle AutoStore and Power Up Recall Software Controlled Store and Recall CycleHardware Store Cycle Switching Waveforms Switching Waveforms AutoStore or Power Up RECALL26 Α α Ordering Information CY14E102L-ZS25XCT CY14E102L-ZS25XITCY14E102N-BA25XCT CY14E102L-BA25XITPart Numbering Nomenclature CY 14 E 102 L ZS P 15 X C TZS Tsop NvsramPackage Diagrams Pin TsopBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Sales, Solutions, and Legal Information Document HistoryOrig. Submission Description of Change