CY62138F MoBL®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.
Storage Temperature | |||
Ambient Temperature with |
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Power Applied | |||
Supply Voltage to Ground |
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Potential | |||
DC Voltage Applied to Outputs |
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in | CCmax | + 0.5V) | |
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Electrical Characteristics (Over the Operating Range)
DC Input Voltage [4, 5] | ||
Output Current into Outputs (LOW) | ............................ 20 mA | |
Static Discharge Voltage | > 2001V | |
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> 200 mA | ||
Operating Range
Device | Range | Ambient | VCC | [6] |
Temperature |
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CY62138FLL | Industrial | 4.5V to 5.5V | ||
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Parameter |
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| Test Conditions |
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| 45 ns |
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| Unit | ||
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| Min | Typ [3] |
| Max |
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VOH | Output HIGH Voltage | IOH = |
| 2.4 |
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| V | |||||
VOL | Output LOW Voltage | IOL = 2.1 mA |
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| 0.4 |
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| V | ||||
VIH | Input HIGH Voltage |
| VCC = 4.5V to 5.5V |
| 2.2 |
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| VCC + 0.5 | V | |||||||
VIL | Input LOW Voltage |
| VCC = 4.5V to 5.5V |
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| 0.8 |
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IIX | Input Leakage Current | GND < VI < VCC |
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| +1 |
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| ∝A | ||||||
IOZ | Output Leakage Current | GND < VO < VCC, Output Disabled |
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| +1 |
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| ∝A | |||||||
ICC | VCC Operating Supply |
| f = fmax = 1/tRC | VCC = VCC(max) |
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| 13 | 18 |
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| Current |
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| IOUT = 0 mA |
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| f = 1 MHz |
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| 1.6 | 2.5 |
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| CMOS levels |
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ISB2 [7] | Automatic CE Power Down |
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| 1 > VCC – 0.2V or CE2 < 0.2V |
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| 1 | 5 |
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| ∝A | ||||
| CE |
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| Current CMOS inputs |
| VIN > VCC – 0.2V or VIN < 0.2V, |
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| f = 0, VCC = VCC(max) |
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Capacitance (For all packages) [8] |
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Parameter |
| Description |
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| Test Conditions |
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| Max |
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CIN |
| Input capacitance |
| TA = 25°C, f = 1 MHz, |
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| 10 |
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| pF | ||
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| VCC = VCC(typ) |
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COUT |
| Output capacitance |
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| 10 |
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| pF | |||
Thermal Resistance [8] |
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Parameter |
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| SOIC |
| TSOP II |
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ΘJA |
| Thermal Resistance |
| Still air, soldered on a 3 × 4.5 inch |
| 44.53 |
| 44.16 |
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| (Junction to Ambient) |
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ΘJC |
| Thermal Resistance |
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| 24.05 |
| 11.97 |
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| (Junction to Case) |
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Notes
4.VIL(min) =
5.VIH(max) = VCC+0.75V for pulse durations less than 20ns.
6.Full device AC operation assumes a 100 ∝s ramp time from 0 to VCC(min) and 200 ∝s wait time after VCC stabilization.
7.Only chip enables (CE1 and CE2) must be at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
8.Tested initially and after any design or process changes that may affect these parameters.
Document #: | Page 3 of 10 |
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