Cypress CY62138F manual Switching Waveforms, Read Cycle No OE controlled 10, 16

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CY62138F MoBL®

Switching Waveforms

Read Cycle 1 (Address transition controlled) [15, 16]

tRC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

Read Cycle No. 2 (OE controlled) [10, 16, 17]

DATA VALID

ADDRESS

 

 

 

 

 

tRC

 

CE

 

 

 

 

tACE

 

 

OE

 

tHZOE

 

 

tDOE

 

 

tHZCE

 

 

tLZOE

HIGH

DATA OUT

HIGH IMPEDANCE

DATA VALID

IMPEDANCE

 

 

tLZCE

 

 

 

tPD

 

V

tPU

ICC

CC

50%

 

50%

SUPPLY

 

CURRENT

 

 

ISB

Write Cycle No. 1 (WE controlled) [10, 14, 18, 19]

 

 

tWC

 

ADDRESS

 

 

 

 

 

tSCE

 

CE

 

 

 

 

tAW

 

tHA

 

tSA

tPWE

 

WE

 

 

 

OE

 

 

 

 

 

tSD

t

 

 

 

HD

DATA IO

NOTE 20

DATA VALID

 

 

tHZOE

 

 

Notes:

15.The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.

16.WE is HIGH for read cycle.

17.Address valid before or similar to CE1 transition LOW and CE2 transition HIGH.

18.Data IO is high impedance if OE = VIH.

19.If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high impedance state.

20.During this period, the IOs are in output state. Do not apply input signals.

Document #: 001-13194 Rev. *A

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Contents Features Logic Block Diagram Functional DescriptionCypress Semiconductor Corporation Pin SOIC/TSOP II Pinout Top View Pin ConfigurationProduct Portfolio Max TypOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings Thermal ResistanceData Retention Waveform Data Retention Characteristics Over the Operating RangeAC Test Loads and Waveforms Parameters UnitParameter Description 45 ns Unit Min Read CycleWrite Cycle Switching Waveforms Read Cycle No OE controlled 10, 16Write Cycle No WE controlled 10, 14, 18 Inputs/Outputs Mode Power Truth TableOrdering Information Package Diagrams Pin 450 Mil Molded SoicPin Tsop II Issue Date Orig. Change Description of Change Document History