Cypress CY62138F manual Truth Table, Ordering Information, Inputs/Outputs Mode Power

Page 7

CY62138F MoBL®

Switching Waveforms (continued)

Write Cycle No. 2 (CE1 or CE2 controlled) [10, 14, 18, 19]

 

tWC

 

ADDRESS

 

 

CE

tSCE

 

 

 

 

tSA

 

 

tAW

tHA

 

tPWE

 

WE

 

 

 

tSD

tHD

DATA IO

DATA VALID

 

 

 

Write Cycle No. 3 (WE controlled, OE LOW) [10, 19]

 

 

tWC

 

ADDRESS

 

 

 

 

 

tSCE

 

CE

 

 

 

 

tAW

 

tHA

 

tSA

tPWE

 

WE

 

 

 

 

 

tSD

tHD

DATA IO

NOTE 20

DATA VALID

 

 

tHZWE

 

tLZWE

Truth Table

CE

WE

OE

Inputs/Outputs

Mode

Power

H

X

X

High Z

Deselect/Power Down

Standby (ISB)

L

H

L

Data Out

Read

Active (ICC)

L

L

X

Data In

Write

Active (ICC)

L

H

H

High Z

Selected, Outputs Disabled

Active (ICC)

Ordering Information

Speed

 

Package

Package Type

Operating

(ns)

Ordering Code

Diagram

Range

 

 

 

 

 

 

45

CY62138FLL-45SXI

51-85081

32-pin Small Outline Integrated Circuit (Pb-free)

Industrial

 

 

 

 

 

 

CY62138FLL-45ZSXI

51-85095

32-pin Thin Small Outline Package II (Pb-free)

 

 

 

 

 

 

Contact your local Cypress sales representative for availability of these parts.

 

Document #: 001-13194 Rev. *A

 

 

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Contents Logic Block Diagram Functional Description FeaturesCypress Semiconductor Corporation Max Typ Pin ConfigurationProduct Portfolio Pin SOIC/TSOP II Pinout Top ViewThermal Resistance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeParameters Unit Data Retention Characteristics Over the Operating RangeAC Test Loads and Waveforms Data Retention WaveformRead Cycle Parameter Description 45 ns Unit MinWrite Cycle Read Cycle No OE controlled 10, 16 Switching WaveformsWrite Cycle No WE controlled 10, 14, 18 Truth Table Inputs/Outputs Mode PowerOrdering Information Pin 450 Mil Molded Soic Package DiagramsPin Tsop II Document History Issue Date Orig. Change Description of Change